[coreboot-gerrit] Patch set updated for coreboot: intel/amenia: Configure the bridge to ChromeEC in the bootblock

[Alexandru Gagniuc (alexandrux.gagniuc@intel.com)]

Alexandru Gagniuc (alexandrux.gagniuc at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14588

-gerrit

commit d2c33ab25413e18c2559056d2c889a1481be99e1
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Tue May 3 11:02:14 2016 -0700

    intel/amenia: Configure the bridge to ChromeEC in the bootblock
    
    Communication with ChromeEC, which is on the LPC bus, is needed early
    on for vboot purposes. I'm not sure if Google wants to have the
    interface available in bootblock or romstage, so we're confguring it
    in the bootblock.
    
    The bridge is automatically reconfigured during ramstage in a way in
    which we don't get duplicate windows opened upt to LPC.
    
    Change-Id: I77887e881d23f655495dec2687394409a5bb8cf5
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/mainboard/intel/amenia/Makefile.inc |  2 ++
 src/mainboard/intel/amenia/bootblock.c  | 31 +++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc
index f05e03b..8d4d5f7 100644
--- a/src/mainboard/intel/amenia/Makefile.inc
+++ b/src/mainboard/intel/amenia/Makefile.inc
@@ -1,3 +1,5 @@
+bootblock-y += bootblock.c
+
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-y += mainboard.c
diff --git a/src/mainboard/intel/amenia/bootblock.c b/src/mainboard/intel/amenia/bootblock.c
new file mode 100644
index 0000000..c483d77
--- /dev/null
+++ b/src/mainboard/intel/amenia/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/lpc.h>
+
+void bootblock_mainboard_init(void)
+{
+	/* Configure pads so that our signals make it out of the SOC. */
+	lpc_configure_pads();
+
+	/* Ports 62/66, 60/64, and 200->208 are needed by ChromeEC */
+	lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
+
+	/* Ports 800 -> 9ff are used by ChromeEC. */
+	lpc_open_pmio_window(0x800, 0x200);
+}