[coreboot-gerrit] New patch to review for coreboot: soc/apollolake/lpc: Allow configuring SERIRQ in continuous mode
Alexandru Gagniuc (alexandrux.gagniuc@intel.com)
gerrit at coreboot.org
Tue May 3 20:29:34 CEST 2016
Alexandru Gagniuc (alexandrux.gagniuc at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14586
-gerrit
commit 7f8fe994ee059de370574917113d5d7338bf189c
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date: Mon Apr 4 10:47:49 2016 -0700
soc/apollolake/lpc: Allow configuring SERIRQ in continuous mode
Every other SOC uses a CONFIG_* flag to enable or disable SERIRQ
continuous mode. Why they do that is beyond me, but the way we
implement it on apollolake is via devicetree.
Change-Id: I6e05758e5e264c6b0015467dd25add3bffe2b040
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
src/soc/intel/apollolake/chip.h | 3 +++
src/soc/intel/apollolake/lpc.c | 23 +++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 9d2bc46..05adef5 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -32,6 +32,9 @@ struct soc_intel_apollolake_config {
uint8_t pcie_rp3_clkreq_pin;
uint8_t pcie_rp4_clkreq_pin;
uint8_t pcie_rp5_clkreq_pin;
+
+ /* Enable continuous mode for LPC SERIRQ line. */
+ bool serirq_continuous_mode;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 58a3cdb..e97f76a 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
+#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
@@ -22,6 +23,8 @@
#include <soc/lpc.h>
#include <soc/pci_ids.h>
+#include "chip.h"
+
/*
* SCOPE:
* The purpose of this driver is to eliminate manual resource allocation for
@@ -40,6 +43,25 @@
* opens up IO and memory windows as needed.
*/
+static void lpc_init(struct device *dev)
+{
+ uint8_t scnt;
+ struct soc_intel_apollolake_config *cfg;
+
+ cfg = dev->chip_info;
+ if (!cfg) {
+ printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+ return;
+ }
+
+ if (cfg->serirq_continuous_mode) {
+ scnt = pci_read_config8(dev, REG_SERIRQ_CTL);
+ scnt |= SCNT_EN | SCNT_MODE;
+ pci_write_config8(dev, REG_SERIRQ_CTL, scnt);
+ }
+
+}
+
static void soc_lpc_add_io_resources(device_t dev)
{
struct resource *res;
@@ -115,6 +137,7 @@ static struct device_operations device_ops = {
.enable_resources = &pci_dev_enable_resources,
.write_acpi_tables = southbridge_write_acpi_tables,
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+ .init = lpc_init,
.scan_bus = scan_lpc_bus,
};
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