[coreboot-gerrit] Patch set updated for coreboot: nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13934

-gerrit

commit 59d0441998a08ae9835e3dfc7efb5edca104b7d9
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Mon Mar 7 14:30:47 2016 -0600

    nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
    
    A couple of arrays were not properly initialized.  This
    did not appear to affect operation of the codebase however
    it led to some ugly values being displayed when debugging
    was turned on.
    
    Also bounds check an array index; as before this did not
    appear to affect operation but was a potential point of
    failure.
    
    Change-Id: I243b7197a74aed78ddca808eb3b0f35f1fe9d95a
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 8597bda..c65e48c 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -1714,6 +1714,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
 		/* 2.10.5.8.3 */
 		Receiver = mct_InitReceiver_D(pDCTstat, dct);
 
+		/* Indicate success unless training the DCT explicitly fails */
 		dct_training_success = 1;
 
 		/* There are four receiver pairs, loosely associated with chipselects.
@@ -1726,8 +1727,9 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
 				continue;
 			}
 
-			for (lane = 0; lane < MAX_BYTE_LANES; lane++)
-				lane_training_success[lane] = 0;
+			/* Initialize variables */
+			memset(lane_training_success, 0, sizeof(lane_training_success));
+			memset(current_phy_phase_delay, 0, sizeof(current_phy_phase_delay));
 
 			/* 2.10.5.8.3 (2) */
 			read_dqs_receiver_enable_control_registers(initial_phy_phase_delay, dev, dct, dimm, index_reg);
@@ -1794,14 +1796,17 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
 #endif
 
 				/* 2.10.5.8.3 (5) */
-				prev = 0;
-				for (current_phy_phase_delay[lane] = rx_en_offset; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) {
+				prev = dqs_results_array[rx_en_offset];
+				for (current_phy_phase_delay[lane] = rx_en_offset + ren_step; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) {
 					if ((dqs_results_array[current_phy_phase_delay[lane]] == 0) && (prev == 1)) {
 						/* Restore last known good delay */
 						current_phy_phase_delay[lane] -= ren_step;
 
 						/* 2.10.5.8.3 (5 A B) */
-						current_phy_phase_delay[lane] -= 0x10;
+						if (current_phy_phase_delay[lane] < 0x10)
+							current_phy_phase_delay[lane] = 0x0;
+						else
+							current_phy_phase_delay[lane] -= 0x10;
 
 						/* Update hardware registers with final values */
 						write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg);