[coreboot-gerrit] Patch set updated for coreboot: nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Wed Mar 9 18:17:55 CET 2016
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13934
-gerrit
commit ed55fb878168f1034e115c3054b75c63ccc9e753
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Mon Mar 7 14:30:47 2016 -0600
nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
A couple of arrays were not properly initialized. This
did not appear to affect operation of the codebase however
it led to some ugly values being displayed when debugging
was turned on.
Also bounds check an array index; as before this did not
appear to affect operation but was a potential point of
failure.
Change-Id: I243b7197a74aed78ddca808eb3b0f35f1fe9d95a
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 35 ++++++++++++++++++--------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 8597bda..716eb56 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -1522,9 +1522,13 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 142 largest read passing region ", best_count, 4);
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4);
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 144 largest read passing region center (raw hardware value) ", region_center, 4);
+
+printk(BIOS_DEBUG, "largest read passing region: %d start: %d\n", best_count, best_pos);
} else {
/* Reprogram the Read DQS Timing Control register with the original settings */
write_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg);
+
+printk(BIOS_DEBUG, "largest read passing region FAILED\n");
}
/* Determine location and length of longest consecutive string of write passing values
@@ -1571,9 +1575,13 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4);
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4);
+
+printk(BIOS_DEBUG, "largest write passing region: %d start: %d\n", best_count, best_pos);
} else {
/* Reprogram the Write DQS Timing Control register with the original settings */
write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg);
+
+printk(BIOS_DEBUG, "largest write passing region FAILED\n");
}
}
@@ -1714,6 +1722,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
/* 2.10.5.8.3 */
Receiver = mct_InitReceiver_D(pDCTstat, dct);
+ /* Indicate success unless training the DCT explicitly fails */
dct_training_success = 1;
/* There are four receiver pairs, loosely associated with chipselects.
@@ -1726,8 +1735,9 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
continue;
}
- for (lane = 0; lane < MAX_BYTE_LANES; lane++)
- lane_training_success[lane] = 0;
+ /* Initialize variables */
+ memset(lane_training_success, 0, sizeof(lane_training_success));
+ memset(current_phy_phase_delay, 0, sizeof(current_phy_phase_delay));
/* 2.10.5.8.3 (2) */
read_dqs_receiver_enable_control_registers(initial_phy_phase_delay, dev, dct, dimm, index_reg);
@@ -1745,13 +1755,13 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
rx_en_offset = (initial_phy_phase_delay[lane] + 0x10) % 0x40;
/* 2.10.5.8.3 (4) */
-#if DQS_TRAIN_DEBUG > 0
+// #if DQS_TRAIN_DEBUG > 0
printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc_D_Fam15 Receiver %d lane %d initial phy delay %04x: iterating from %04x to %04x\n", Receiver, lane, initial_phy_phase_delay[lane], rx_en_offset, 0x3ff);
-#endif
+// #endif
for (current_phy_phase_delay[lane] = rx_en_offset; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) {
-#if DQS_TRAIN_DEBUG > 0
+// #if DQS_TRAIN_DEBUG > 0
printk(BIOS_DEBUG, "%s: Receiver %d lane %d current phy delay: %04x\n", __func__, Receiver, lane, current_phy_phase_delay[lane]);
-#endif
+// #endif
/* 2.10.5.8.3 (4 A) */
write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg);
@@ -1794,14 +1804,17 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
#endif
/* 2.10.5.8.3 (5) */
- prev = 0;
- for (current_phy_phase_delay[lane] = rx_en_offset; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) {
+ prev = dqs_results_array[rx_en_offset];
+ for (current_phy_phase_delay[lane] = rx_en_offset + ren_step; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) {
if ((dqs_results_array[current_phy_phase_delay[lane]] == 0) && (prev == 1)) {
/* Restore last known good delay */
current_phy_phase_delay[lane] -= ren_step;
/* 2.10.5.8.3 (5 A B) */
- current_phy_phase_delay[lane] -= 0x10;
+ if (current_phy_phase_delay[lane] < 0x10)
+ current_phy_phase_delay[lane] = 0x0;
+ else
+ current_phy_phase_delay[lane] -= 0x10;
/* Update hardware registers with final values */
write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg);
@@ -1823,13 +1836,13 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
}
}
-#if DQS_TRAIN_DEBUG > 0
+// #if DQS_TRAIN_DEBUG > 0
printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc_D_Fam15 DQS receiver enable timing: ");
for (lane = 0; lane < MAX_BYTE_LANES; lane++) {
printk(BIOS_DEBUG, " %03x", current_phy_phase_delay[lane]);
}
printk(BIOS_DEBUG, "\n");
-#endif
+// #endif
}
if (!dct_training_success) {
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