[coreboot-gerrit] New patch to review for coreboot: nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Sat Jun 18 17:57:59 CEST 2016
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15257
-gerrit
commit d70a8743ac3ce15eaec1c243b6e442848801c8c6
Author: Damien Zammit <damien at zamaudio.com>
Date: Sat Jun 18 23:57:43 2016 +1000
nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM
Previously, any 800MHz dimms were being slowed to 667MHz
for no reason other than there was a bug in the maximum
frequency detection code for the MCH.
This change also removes some unused DDR3 detection code.
Change-Id: Id6c6c88c4a40631f6caf52f536a939a43cb3faf1
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/northbridge/intel/x4x/raminit.c | 50 +++----------------------------------
1 file changed, 4 insertions(+), 46 deletions(-)
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 4f5575c..7ab4697 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -297,7 +297,6 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
u8 cas;
u8 lowcas;
u8 highcas;
- u8 maxfreq;
u8 freq = 0;
// Find max FSB speed
@@ -317,19 +316,11 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
break;
}
- // Find RAM speed
- maxfreq = (u8) ((pci_read_config16(PCI_DEV(0,0,0), 0xea) >> 4) & 0x3f);
+ // Max RAM speed
if (s->spd_type == DDR2) {
- // Limit frequency for MCH
- maxfreq &= 0x7;
+ // Choose max memory frequency for MCH : 800MHz
freq = MEM_CLOCK_800MHz;
- if (maxfreq) {
- freq = maxfreq;
- }
- if (freq > MEM_CLOCK_800MHz) {
- freq = MEM_CLOCK_800MHz;
- }
// Detect a common CAS latency
commoncas = 0xff;
@@ -408,41 +399,8 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
}
s->selected_timings.mem_clk = freq;
s->selected_timings.CAS = cas;
-
- } else { // DDR3
- // Limit frequency for MCH
- maxfreq >>= 3;
- freq = MEM_CLOCK_1333MHz;
- if (maxfreq) {
- freq = maxfreq + 2;
- }
- if (freq > MEM_CLOCK_1333MHz) {
- freq = MEM_CLOCK_1333MHz;
- }
-
- // Limit DDR speed to FSB speed
- switch (s->max_fsb) {
- case FSB_CLOCK_800MHz:
- if (freq > MEM_CLOCK_800MHz) {
- freq = MEM_CLOCK_800MHz;
- }
- break;
- case FSB_CLOCK_1066MHz:
- if (freq > MEM_CLOCK_1066MHz) {
- freq = MEM_CLOCK_1066MHz;
- }
- break;
- case FSB_CLOCK_1333MHz:
- if (freq > MEM_CLOCK_1333MHz) {
- freq = MEM_CLOCK_1333MHz;
- }
- break;
- default:
- die("Invalid FSB\n");
- break;
- }
-
- // TODO: CAS detection for DDR3
+ } else {
+ die("Wrong DDR type\n");
}
}
More information about the coreboot-gerrit
mailing list