[coreboot-gerrit] New patch to review for coreboot: intel/apollolake: Enable upper CMOS bank in bootblock
Furquan Shaikh (furquan@google.com)
gerrit at coreboot.org
Sun Jul 31 03:29:05 CEST 2016
Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15998
-gerrit
commit 138bd5deebd6e311be9ea1ae251f7e7d6eb465ab
Author: Furquan Shaikh <furquan at google.com>
Date: Sat Jul 30 18:06:23 2016 -0700
intel/apollolake: Enable upper CMOS bank in bootblock
Upper CMOS bank is used to store the boot count. It is important to
enable it as soon as possible in bootblock.
BUG=chrome-os-partner:55473
Change-Id: I7c4f49c337c2e24a93c1e71466e2f66db04be562
Signed-off-by: Furquan Shaikh <furquan at google.com>
---
src/soc/intel/apollolake/bootblock/bootblock.c | 10 ++++++++++
src/soc/intel/apollolake/include/soc/iosf.h | 4 ++++
2 files changed, 14 insertions(+)
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 31144ff..3015d17 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -22,6 +22,7 @@
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/gpio.h>
+#include <soc/iosf.h>
#include <soc/mmap_boot.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
@@ -56,6 +57,13 @@ static void enable_pm_timer(void)
wrmsr(MSR_EMULATE_PM_TMR, msr);
}
+static void enable_cmos_upper_bank(void)
+{
+ uint32_t reg = iosf_read(IOSF_RTC_PORT_ID, RTC_CONFIG);
+ reg |= RTC_CONFIG_UCMOS_ENABLE;
+ iosf_write(IOSF_RTC_PORT_ID, RTC_CONFIG, reg);
+}
+
void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
{
device_t dev = NB_DEV_ROOT;
@@ -82,6 +90,8 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MASTER);
+ enable_cmos_upper_bank();
+
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(base_timestamp);
}
diff --git a/src/soc/intel/apollolake/include/soc/iosf.h b/src/soc/intel/apollolake/include/soc/iosf.h
index eeb9330..ae3e8ec 100644
--- a/src/soc/intel/apollolake/include/soc/iosf.h
+++ b/src/soc/intel/apollolake/include/soc/iosf.h
@@ -20,6 +20,10 @@
#include <arch/io.h>
+#define IOSF_RTC_PORT_ID 0xD1
+#define RTC_CONFIG 0x3400
+#define RTC_CONFIG_UCMOS_ENABLE (1 << 2)
+
inline static void iosf_write(uint16_t port, uint16_t reg, uint32_t val)
{
uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3);
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