[coreboot-gerrit] New patch to review for coreboot: mainboard/elmex: Add new board pcm205401
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Thu Jul 28 15:29:45 CEST 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15930
-gerrit
commit 60e980bbbee49737bd00a095b7f2765d17682249
Author: Yuichi Ito <yui.corebt at gmail.com>
Date: Thu Jul 28 13:34:18 2016 +0900
mainboard/elmex: Add new board pcm205401
Change-Id: I6c7e90db84f13ffbf9e629f2b92649895a466155
Signed-off-by: Yuichi Ito <yui.corebt at gmail.com>
---
src/mainboard/elmex/pcm205401/BiosCallOuts.c | 34 ++---
src/mainboard/elmex/pcm205401/Kconfig | 7 +-
src/mainboard/elmex/pcm205401/OemCustomize.c | 138 ++++++++++++++-------
.../elmex/pcm205401/PlatformGnbPcieComplex.h | 110 ++++++++++------
src/mainboard/elmex/pcm205401/SBCimxPcieReset.h | 17 +++
src/mainboard/elmex/pcm205401/buildOpts.c | 67 +++++-----
src/mainboard/elmex/pcm205401/devicetree.cb | 6 +-
src/mainboard/elmex/pcm205401/irq_tables.c | 3 +-
src/mainboard/elmex/pcm205401/mainboard.c | 86 ++++++++-----
src/mainboard/elmex/pcm205401/mptable.c | 24 ++--
src/mainboard/elmex/pcm205401/platform_cfg.h | 10 +-
src/mainboard/elmex/pcm205401/romstage.c | 13 +-
12 files changed, 321 insertions(+), 194 deletions(-)
diff --git a/src/mainboard/elmex/pcm205401/BiosCallOuts.c b/src/mainboard/elmex/pcm205401/BiosCallOuts.c
index 9a2a9bb..497ec58 100644
--- a/src/mainboard/elmex/pcm205401/BiosCallOuts.c
+++ b/src/mainboard/elmex/pcm205401/BiosCallOuts.c
@@ -20,11 +20,12 @@
#include "SB800.h"
#include <stdlib.h>
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func,
+ UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func,
+ UINTN Data, VOID *ConfigPtr);
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD, agesa_ReadSpd },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
@@ -37,17 +38,19 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+/* Call the host environment interface to provide a user hook opportunity. */
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func,
+ UINTN Data, VOID *ConfigPtr)
{
// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
// Make sure the right speed settings are selected.
- ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
+ ((MEM_DATA_STRUCT *)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
return AGESA_SUCCESS;
}
/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func,
+ UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
@@ -63,27 +66,26 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
// Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
- Data16=Data8<<8;
+ Data16 = Data8<<8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
- Data16|=Data8;
+ Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- switch (ResetInfo->ResetId)
- {
- case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
+ switch (ResetInfo->ResetId) {
+ case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
- Data8 &= ~(UINT8)BIT6 ;
+ Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
- Data8 |= BIT6 ;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
+ Data8 |= BIT6;
+ Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
Status = AGESA_SUCCESS;
break;
}
diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig
index e80e68b..a5f7426 100644
--- a/src/mainboard/elmex/pcm205401/Kconfig
+++ b/src/mainboard/elmex/pcm205401/Kconfig
@@ -61,14 +61,9 @@ config VGA_BIOS
bool
default n
-#config VGA_BIOS_FILE
-# string "VGA BIOS path and filename"
-# depends on VGA_BIOS
-# default "rom/video/OntarioGenericVbios.bin"
-
config VGA_BIOS_ID
string
- default "1002,9802"
+ default "1002,9804" # FUSION_G_T40R
config SB800_AHCI_ROM
bool
diff --git a/src/mainboard/elmex/pcm205401/OemCustomize.c b/src/mainboard/elmex/pcm205401/OemCustomize.c
index 825364e..803dbf6 100644
--- a/src/mainboard/elmex/pcm205401/OemCustomize.c
+++ b/src/mainboard/elmex/pcm205401/OemCustomize.c
@@ -23,20 +23,20 @@
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/**
- * OemCustomizeInitEarly
+ * OemCustomizeInitEarly
*
- * Description:
- * This stub function will call the host environment through the binary block
- * interface (call-out port) to provide a user hook opportunity
+ * Description:
+ * This stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
*
- * Parameters:
- * @param[in] *InitEarly
+ * Parameters:
+ * @param[in] *InitEarly
*
- * @retval VOID
+ * @retval VOID
*
**/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -45,52 +45,87 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams;
-PCIe_PORT_DESCRIPTOR PortList [] = {
- // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+PCIe_PORT_DESCRIPTOR PortList[] = {
+// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+ PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT,
+ GNB_GPP_PORT4_CHANNEL_TYPE,
+ 4,
+ GNB_GPP_PORT4_HOTPLUG_SUPPORT,
+ GNB_GPP_PORT4_SPEED_MODE,
+ GNB_GPP_PORT4_SPEED_MODE,
+ GNB_GPP_PORT4_LINK_ASPM,
+ 46)
},
- // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+ PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT,
+ GNB_GPP_PORT5_CHANNEL_TYPE,
+ 5,
+ GNB_GPP_PORT5_HOTPLUG_SUPPORT,
+ GNB_GPP_PORT5_SPEED_MODE,
+ GNB_GPP_PORT5_SPEED_MODE,
+ GNB_GPP_PORT5_LINK_ASPM,
+ 46)
},
- // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT,
+ GNB_GPP_PORT6_CHANNEL_TYPE,
+ 6,
+ GNB_GPP_PORT6_HOTPLUG_SUPPORT,
+ GNB_GPP_PORT6_SPEED_MODE,
+ GNB_GPP_PORT6_SPEED_MODE,
+ GNB_GPP_PORT6_LINK_ASPM,
+ 46)
},
- // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+ PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT,
+ GNB_GPP_PORT7_CHANNEL_TYPE,
+ 7,
+ GNB_GPP_PORT7_HOTPLUG_SUPPORT,
+ GNB_GPP_PORT7_SPEED_MODE,
+ GNB_GPP_PORT7_SPEED_MODE,
+ GNB_GPP_PORT7_LINK_ASPM,
+ 0)
},
- // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT,
+ GNB_GPP_PORT8_CHANNEL_TYPE,
+ 8,
+ GNB_GPP_PORT8_HOTPLUG_SUPPORT,
+ GNB_GPP_PORT8_SPEED_MODE,
+ GNB_GPP_PORT8_SPEED_MODE,
+ GNB_GPP_PORT8_LINK_ASPM,
+ 0)
}
};
-PCIe_DDI_DESCRIPTOR DdiList [] = {
- // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+PCIe_DDI_DESCRIPTOR DdiList[] = {
+// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
- //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+ //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeLvds, Aux1, Hdp1}
},
- // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
{
DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
- //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+ //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
{ConnectorTypeDP, Aux2, Hdp2}
}
};
@@ -105,50 +140,57 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
// GNB PCIe topology Porting
//
- // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+ // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR,
+ // PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
- AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
+ AllocHeapParams.RequestedBufferSize = sizeof(Brazos) +
+ sizeof(PortList) +
+ sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+ Status = HeapAllocateBuffer(&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
- BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+ BrazosPcieComplexListPtr =
+ (PCIe_COMPLEX_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
- BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+ BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
- BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+ BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *)AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
- ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
- ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+ ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->PciePortList =
+ (PCIe_PORT_DESCRIPTOR *)BrazosPciePortPtr;
+ ((PCIe_COMPLEX_DESCRIPTOR *)BrazosPcieComplexListPtr)->DdiLinkList =
+ (PCIe_DDI_DESCRIPTOR *)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
return AGESA_SUCCESS;
}
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
+/*-----------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *-----------------------------------------------------------------------------
*/
/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform
+ * information to AGESA (e.g. MemClk routing, the number of DIMM slots
+ * per channel,...). If PlatformSpecificTable is populated, AGESA will
+ * base its settings on the data from the table. Otherwise, it will use
+ * its default conservative settings.
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END
};
diff --git a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h
index 4132c7c..a713f0d 100644
--- a/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h
+++ b/src/mainboard/elmex/pcm205401/PlatformGnbPcieComplex.h
@@ -21,45 +21,85 @@
#include "amdlib.h"
#include <cpu/amd/agesa/s3_resume.h>
-//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/*
+ * GNB GPP Port4
+ * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable
+ * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
+ * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
+ * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
+ * 2:Half-swing(0db) 3:Half-swing(-3.5db)
+ * 4:extended length(-6db) 5:extended length(-8db)
+ * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
+ */
+#define GNB_GPP_PORT4_PORT_PRESENT 1
+#define GNB_GPP_PORT4_SPEED_MODE 2
+#define GNB_GPP_PORT4_LINK_ASPM 3
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0
-//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/*
+ * GNB GPP Port5
+ * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable
+ * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
+ * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
+ * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
+ * 2:Half-swing(0db) 3:Half-swing(-3.5db)
+ * 4:extended length(-6db) 5:extended length(-8db)
+ * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
+ */
+#define GNB_GPP_PORT5_PORT_PRESENT 1
+#define GNB_GPP_PORT5_SPEED_MODE 2
+#define GNB_GPP_PORT5_LINK_ASPM 3
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0
-//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/*
+ * GNB GPP Port6
+ * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable
+ * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
+ * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
+ * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
+ * 2:Half-swing(0db) 3:Half-swing(-3.5db)
+ * 4:extended length(-6db) 5:extended length(-8db)
+ * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
+ */
+#define GNB_GPP_PORT6_PORT_PRESENT 1
+#define GNB_GPP_PORT6_SPEED_MODE 2
+#define GNB_GPP_PORT6_LINK_ASPM 3
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0
-//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/*
+ * GNB GPP Port7
+ * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable
+ * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
+ * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
+ * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
+ * 2:Half-swing(0db) 3:Half-swing(-3.5db)
+ * 4:extended length(-6db) 5:extended length(-8db)
+ * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
+ */
+#define GNB_GPP_PORT7_PORT_PRESENT 0
+#define GNB_GPP_PORT7_SPEED_MODE 2
+#define GNB_GPP_PORT7_LINK_ASPM 3
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0
-//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+/*
+ * GNB GPP Port8
+ * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable
+ * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
+ * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
+ * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
+ * 2:Half-swing(0db) 3:Half-swing(-3.5db)
+ * 4:extended length(-6db) 5:extended length(-8db)
+ * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
+ */
+#define GNB_GPP_PORT8_PORT_PRESENT 1
+#define GNB_GPP_PORT8_SPEED_MODE 2
+#define GNB_GPP_PORT8_LINK_ASPM 3
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h b/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h
new file mode 100644
index 0000000..e6c126a
--- /dev/null
+++ b/src/mainboard/elmex/pcm205401/SBCimxPcieReset.h
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 ELMEX Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
diff --git a/src/mainboard/elmex/pcm205401/buildOpts.c b/src/mainboard/elmex/pcm205401/buildOpts.c
index fe4e779..fa4fc0d 100644
--- a/src/mainboard/elmex/pcm205401/buildOpts.c
+++ b/src/mainboard/elmex/pcm205401/buildOpts.c
@@ -102,8 +102,8 @@
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
#define BLDCFG_VRM_CURRENT_LIMIT 24000
//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
@@ -130,9 +130,9 @@
#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
-#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList)
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
//#define BLDCFG_ALLOCATED_BUSNUMS 0x20
@@ -171,12 +171,12 @@
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
#define BLDCFG_MEMORY_POWER_DOWN TRUE
-#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
//#define BLDCFG_ONLINE_SPARE FALSE
//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
#define BLDCFG_BANK_SWIZZLE TRUE
-#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
#define BLDCFG_USE_BURST_MODE FALSE
@@ -206,8 +206,7 @@
#include "AGESA.h"
/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
+CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = {
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
@@ -222,7 +221,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
{ CPU_LIST_TERMINAL }
};
-/* Include the files that instantiate the configuration definitions. */
+/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
@@ -247,7 +246,8 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
+ * should also be updated/incremented for the next expected version,
+ * + trailing 'X'
****************************************************************************/
// This is the delivery package title, "BrazosPI"
// This string MUST be exactly 8 characters long
@@ -255,35 +255,38 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
+#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0',\
+ '.', '3', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY 200 ///< DDR 400
-#define DDR533_FREQUENCY 266 ///< DDR 533
-#define DDR667_FREQUENCY 333 ///< DDR 667
-#define DDR800_FREQUENCY 400 ///< DDR 800
-#define DDR1066_FREQUENCY 533 ///< DDR 1066
-#define DDR1333_FREQUENCY 667 ///< DDR 1333
-#define DDR1600_FREQUENCY 800 ///< DDR 1600
-#define DDR1866_FREQUENCY 933 ///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/* The following definitions specify the default values for various parameters
+ * in which there are no clearly defined defaults to be used in the common
+ * file. The values below are based on product and BKDG content, please consult
+ * the AGESA Memory team for consultation.
+ */
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
diff --git a/src/mainboard/elmex/pcm205401/devicetree.cb b/src/mainboard/elmex/pcm205401/devicetree.cb
index afab841..6269d09 100644
--- a/src/mainboard/elmex/pcm205401/devicetree.cb
+++ b/src/mainboard/elmex/pcm205401/devicetree.cb
@@ -47,7 +47,8 @@ chip northbridge/amd/agesa/family14/root_complex
end
end # SM
device pci 14.1 on end # IDE 0x439c
- device pci 14.2 on end # HDA 0x4383
+# HDA is not used on board.
+ device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81865f
device pnp 4e.0 off # Floppy
@@ -57,7 +58,8 @@ chip northbridge/amd/agesa/family14/root_complex
end
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 off end # Hardware Monitor
- device pnp 4e.5 on # Keyboard
+# Keyboard interface on superI/O is not used.
+ device pnp 4e.5 off # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
diff --git a/src/mainboard/elmex/pcm205401/irq_tables.c b/src/mainboard/elmex/pcm205401/irq_tables.c
index 0c53417..e4746f7 100644
--- a/src/mainboard/elmex/pcm205401/irq_tables.c
+++ b/src/mainboard/elmex/pcm205401/irq_tables.c
@@ -100,9 +100,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
+ if (sum != pirq->checksum)
pirq->checksum = sum;
- }
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
diff --git a/src/mainboard/elmex/pcm205401/mainboard.c b/src/mainboard/elmex/pcm205401/mainboard.c
index e0440f2..27ee53c 100644
--- a/src/mainboard/elmex/pcm205401/mainboard.c
+++ b/src/mainboard/elmex/pcm205401/mainboard.c
@@ -29,9 +29,7 @@
#include "SBPLATFORM.h"
#include <southbridge/amd/cimx/sb800/pci_devs.h>
#include <northbridge/amd/agesa/family14/pci_devs.h>
-
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
+#include "SBCimxPcieReset.h"
/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -50,36 +48,36 @@ void set_pcie_dereset(void);
*/
static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
/* INTA# - INTH# */
- [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
+ [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B,
/* Misc-nil,0,1,2, INT from Serial irq */
- [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ [0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
- [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
+ [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F,
/* IMC INT0 - 5 */
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
/* USB Devs 18/19/20/22 INTA-C */
- [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
+ [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A,
/* IDE, SATA */
- [0x40] = 0x0B,0x0B,
+ [0x40] = 0x0B, 0x0B,
/* GPPInt0 - 3 */
- [0x50] = 0x0A,0x0B,0x0A,0x0B
+ [0x50] = 0x0A, 0x0B, 0x0A, 0x0B
};
static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
/* INTA# - INTH# */
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
/* Misc-nil,0,1,2, INT from Serial irq */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F,
/* IMC INT0 - 5 */
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
/* USB Devs 18/19/22/20 INTA-C */
- [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
+ [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12,
/* IDE, SATA */
- [0x40] = 0x11,0x13,
+ [0x40] = 0x11, 0x13,
/* GPPInt0 - 3 */
- [0x50] = 0x10,0x11,0x12,0x13
+ [0x50] = 0x10, 0x11, 0x12, 0x13
};
/*
@@ -99,30 +97,48 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
* off-chip devices should get mapped to PIRQH/E/F/G.
*/
+/*
+ * GFX_DEVFN VGA: 01.0
+ * NB_PCIE_PORT1_DEVFN NIC: 04.0
+ * NB_PCIE_PORT3_DEVFN PCIe bdg: 06.0
+ * SATA_DEVFN SATA: 11.0
+ * OHCI1_DEVFN OHCI1: 12.0
+ * EHCI1_DEVFN EHCI1: 12.2
+ * OHCI2_DEVFN OHCI2: 13.0
+ * EHCI2_DEVFN EHCI2: 13.2
+ * SMBUS_DEVFN SMBUS: 14.0
+ * IDE_DEVFN IDE: 14.1
+ * HDA_DEVFN HDA: 14.2
+ * SB_PCI_PORT_DEVFN PCI bdg: 14.4
+ * OHCI4_DEVFN OHCI4: 14.5
+ * OHCI3_DEVFN OHCI3: 16.0
+ * EHCI3_DEVFN EHCI3: 16.2
+ */
static const struct pirq_struct mainboard_pirq_data[] = {
/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
- {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
- {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */
- {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */
- {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
- {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
- {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
- {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
- {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
- {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
- {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */
- {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
- {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */
- {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */
- {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */
- {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */
+ {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC} },
+ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
+ {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
+ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} },
+ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} },
+ {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} },
+ {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} },
+ {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} },
+ {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} },
+ {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC} },
+ {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} },
+ {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G} },
+ {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} },
+ {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} },
+ {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} },
};
/* PIRQ Setup */
static void pirq_setup(void)
{
pirq_data_ptr = mainboard_pirq_data;
- pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
+ pirq_data_size = sizeof(mainboard_pirq_data)
+ / sizeof(struct pirq_struct);
intr_data_ptr = mainboard_intr_data;
picr_data_ptr = mainboard_picr_data;
}
@@ -149,11 +165,13 @@ void set_pcie_dereset(void)
**********************************************/
static void mainboard_enable(device_t dev)
{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ printk(BIOS_INFO,
+ "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/* enable GPP CLK0 thru CLK1 */
/* disable GPP CLK2 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
+
write8(misc_mem_clk_cntrl + 0, 0xFF);
write8(misc_mem_clk_cntrl + 1, 0x00);
write8(misc_mem_clk_cntrl + 2, 0x00);
diff --git a/src/mainboard/elmex/pcm205401/mptable.c b/src/mainboard/elmex/pcm205401/mptable.c
index 8e954cd..04a9ade 100644
--- a/src/mainboard/elmex/pcm205401/mptable.c
+++ b/src/mainboard/elmex/pcm205401/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -76,7 +76,8 @@ static void *smp_write_config_table(void *v)
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
+ (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
@@ -110,13 +111,18 @@ static void *smp_write_config_table(void *v)
/* PCI slots */
device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ //INTA -> INTE
+ PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
+ //INTB -> INTF
+ PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
+ //INTC -> INTG
+ PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
+ //INTD -> INTH
+ PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
}
/* PCIe PortA */
@@ -128,9 +134,10 @@ static void *smp_write_config_table(void *v)
/* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE |\
+ MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin))
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
@@ -143,6 +150,7 @@ static void *smp_write_config_table(void *v)
unsigned long write_smp_table(unsigned long addr)
{
void *v;
+
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
return (unsigned long)smp_write_config_table(v);
}
diff --git a/src/mainboard/elmex/pcm205401/platform_cfg.h b/src/mainboard/elmex/pcm205401/platform_cfg.h
index 660be41..a7de71b 100644
--- a/src/mainboard/elmex/pcm205401/platform_cfg.h
+++ b/src/mainboard/elmex/pcm205401/platform_cfg.h
@@ -208,8 +208,7 @@
*/
#define GEC_CONFIG 0
-static const CODECENTRY persimmon_codec_alc269[] =
-{
+static const CODECENTRY persimmon_codec_alc269[] = {
/* NID, PinConfig */
{0x12, 0x411111F0},
{0x14, 0x99130110},
@@ -225,10 +224,9 @@ static const CODECENTRY persimmon_codec_alc269[] =
{0xff, 0xffffffff} /* end of table */
};
-static const CODECTBLLIST codec_tablelist[] =
-{
- {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
- {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}
+static const CODECTBLLIST codec_tablelist[] = {
+ {0x010ec0269, (CODECENTRY *)&persimmon_codec_alc269[0]},
+ {0x0FFFFFFFFUL, (CODECENTRY *)0x0FFFFFFFFUL}
};
/**
diff --git a/src/mainboard/elmex/pcm205401/romstage.c b/src/mainboard/elmex/pcm205401/romstage.c
index 0aad4f5..aef9d04 100644
--- a/src/mainboard/elmex/pcm205401/romstage.c
+++ b/src/mainboard/elmex/pcm205401/romstage.c
@@ -50,11 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
* All cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
*/
- __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
+ __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
+ __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
- /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
- __writemsr (0xc0010062, 0);
+ /* All cores: set pstate 0 (1600 MHz) early to save a few ms of
+ * boot time
+ */
+ __writemsr(0xc0010062, 0);
amd_initmmio();
@@ -83,6 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
+
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
@@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
agesawrapper_amdinitenv();
amd_initenv();
- } else { /* S3 detect */
+ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
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