[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Add C entry bootblock support

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e4a8537ce20d801a5985ba6268ae83593063a4bf
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Sun Jul 24 00:36:12 2016 +0530

    soc/intel/skylake: Add C entry bootblock support
    
    List of activity performing in this patch
    - early PCH programming
    - early SA programming
    - early CPU programming
    - mainborad early gpio programming for UART and SPI
    - car setup
    - move chipset programming from verstage to post console
    
    BUG=chrome-os-partner:55357
    BRANCH=none
    TEST=Built and booted kunimitsu till POST code 0x34
    
    Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Reviewed-on: https://review.coreboot.org/15785
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15785 for details.

-gerrit