[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Do cache as ram and prepare for C entry

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 68d5d8b28ab399b8dfb8ef6477d25311a319f2d5
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Mon Jul 18 14:13:52 2016 +0530

    soc/intel/skylake: Do cache as ram and prepare for C entry
    
    Enable cache-as-ram and prepare for c entry in bootblock.
    
    BUG=chrome-os-partner:55357
    BRANCH=none
    TEST=Built and booted kunimitsu till POST code 0x2A
    
    Credits-to: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    
    Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1
    Reviewed-on: https://review.coreboot.org/15784
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15784 for details.

-gerrit