[coreboot-gerrit] Patch merged into coreboot/master: google/oak: dsi: set mipi pin driving control on
gerrit at coreboot.org
gerrit at coreboot.org
Tue Jul 26 17:49:08 CEST 2016
the following patch was just integrated into master:
commit c7dfbe26fd2baf373a439fa5edfe23da9a25c8b7
Author: Martin Roth <martinroth at chromium.org>
Date: Fri Jul 22 11:15:12 2016 -0600
google/oak: dsi: set mipi pin driving control on
We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.
When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown(floating). This creates a chance that MIPI
output would be influenced. The DSI's LP signal will be half voltage
attenuation. There will be no display on panel.
When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.
We only need to set this register once, so we set it here to prevent
repeat setting in the kernel when the system goes to recovery mode.
BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui
The original commit in the cros repo combined the chipset and mainboard
code changes. This has been split for the push to coreboot.org
Change-Id: I733bdd115950b71493856220414ac0dd75d28122
Signed-off-by: Martin Roth <martinroth at chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi at mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi at mediatek.com>
Original-Tested-by: jitao shi <jitao.shi at mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Reviewed-on: https://review.coreboot.org/15808
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan at google.com>
See https://review.coreboot.org/15808 for details.
-gerrit
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