[coreboot-gerrit] Patch merged into coreboot/master: meditek/mt8173: dsi: set mipi pin driving control on

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 700b03962baac585c0c0dc1df764da5664574291
Author: Jitao Shi <jitao.shi at mediatek.com>
Date:   Fri Jul 15 14:23:53 2016 +0800

    meditek/mt8173: dsi: set mipi pin driving control on
    
    We set this driving control to prevent signal attenuation caused by
    LVDS DRV termination.
    
    When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
    termination status is unknown (floating). This creates a chance that
    MIPI output would be influenced. The DSI's LP signal will be half
    voltage attenuation. There will be no display on panel.
    
    When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
    effective and termination is fixed OFF. The DSI won't be influenced.
    
    We only need to set this register once, so we set it here to prevent
    repeatedly setting in the kernel when the system goes to recovery mode.
    
    BUG=chrome-os-partner:55296
    BRANCH=none
    TEST=build pass elm and show ui
    
    Change-Id: Ie3ccf6fb611dd5a1e2c02b7825d42a92e61268c0
    Signed-off-by: Martin Roth <martinroth at chromium.org>
    Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
    Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
    Original-Signed-off-by: Jitao Shi <jitao.shi at mediatek.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/360850
    Original-Commit-Ready: jitao shi <jitao.shi at mediatek.com>
    Original-Tested-by: jitao shi <jitao.shi at mediatek.com>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: https://review.coreboot.org/15807
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See https://review.coreboot.org/15807 for details.

-gerrit