[coreboot-gerrit] New patch to review for coreboot: soc/intel/quark: Initialize MTRRs in bootblock

[Lee Leahy (leroy.p.leahy@intel.com)]

Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15861

-gerrit

commit fda187d0171de7183fc7a6fd9b8a8cfb8261f290
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Mon Jul 25 07:11:05 2016 -0700

    soc/intel/quark: Initialize MTRRs in bootblock
    
    Initialize the MTRRs for use by bootblock and romstage.
    
    TEST=Build and run on Galileo Gen2.
    
    Change-Id: Ib1d422c738820163f54771c65034ae77301237ec
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/quark/bootblock/bootblock.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c
index 4aa774b..6e036d8 100644
--- a/src/soc/intel/quark/bootblock/bootblock.c
+++ b/src/soc/intel/quark/bootblock/bootblock.c
@@ -18,6 +18,7 @@
 #include <device/pci_def.h>
 #include <program_loading.h>
 #include <soc/iomap.h>
+#include <soc/intel/common/util.h>
 #include <soc/pci_devs.h>
 #include <soc/reg_access.h>
 
@@ -47,8 +48,26 @@ static const struct reg_script hsuart_init[] = {
 	REG_SCRIPT_END
 };
 
+static const struct reg_script mtrr_init[] = {
+	/* Cache the SPI flash */
+	REG_MTRR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE)
+		| MTRR_TYPE_WRBACK)),
+	REG_MTRR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE)
+		| MTRR_PHYS_MASK_VALID)),
+
+	/* Cache ESRAM */
+	REG_MTRR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000
+		| MTRR_TYPE_WRBACK)),
+	REG_MTRR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff)
+		| MTRR_PHYS_MASK_VALID)),
+	REG_SCRIPT_END
+};
+
 void bootblock_soc_early_init(void)
 {
+	/* Initialize the MTRRs */
+	reg_script_run(mtrr_init);
+
 	/* Initialize the controllers */
 	reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
 	reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);