[coreboot-gerrit] New patch to review for coreboot: soc/intel/quark: Add MTTR support to register scripts
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Mon Jul 25 21:39:46 CEST 2016
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15860
-gerrit
commit 1507fdece423994b297342455c9887de6ec02c23
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sun Jul 24 09:24:43 2016 -0700
soc/intel/quark: Add MTTR support to register scripts
Add MTRR access to register scripts. Migrate the code from mtrr.c
into reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: I5f00d548283c44d0d9b03e78de7376756cee3daf
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/quark/include/soc/reg_access.h | 28 +++++++
src/soc/intel/quark/include/soc/romstage.h | 2 -
src/soc/intel/quark/reg_access.c | 119 +++++++++++++++++++++++++++
src/soc/intel/quark/romstage/mtrr.c | 109 ++----------------------
4 files changed, 153 insertions(+), 105 deletions(-)
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index 8a18333..317742d 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -19,6 +19,8 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
#include <delay.h>
#include <fsp/util.h>
#include <reg_script.h>
@@ -37,6 +39,7 @@ enum {
PCIE_RESET,
GPE0_REGS,
HOST_BRIDGE,
+ MTRR_REGS,
};
enum {
@@ -132,6 +135,27 @@ enum {
#define REG_LEG_GPIO_XOR(reg_, value_) \
REG_LEG_GPIO_RXW(reg_, 0xffffffff, value_)
+/* MTRR register access macros */
+#define REG_MTRR_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
+ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
+ MTRR_REGS)
+#define REG_MTRR_READ(reg_) \
+ REG_MTRR_ACCESS(READ, reg_, 0, 0, 0)
+#define REG_MTRR_WRITE(reg_, value_) \
+ REG_MTRR_ACCESS(WRITE, reg_, 0, value_, 0)
+#define REG_MTRR_AND(reg_, value_) \
+ REG_MTRR_RMW(reg_, value_, 0)
+#define REG_MTRR_RMW(reg_, mask_, value_) \
+ REG_MTRR_ACCESS(RMW, reg_, mask_, value_, 0)
+#define REG_MTRR_RXW(reg_, mask_, value_) \
+ REG_MTRR_ACCESS(RXW, reg_, mask_, value_, 0)
+#define REG_MTRR_OR(reg_, value_) \
+ REG_MTRR_RMW(reg_, 0xffffffff, value_)
+#define REG_MTRR_POLL(reg_, mask_, value_, timeout_) \
+ REG_MTRR_ACCESS(POLL, reg_, mask_, value_, timeout_)
+#define REG_MTRR_XOR(reg_, value_) \
+ REG_MTRR_RXW(reg_, 0xffffffff, value_)
+
/* PCIE AFE register access macros */
#define REG_PCIE_AFE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
@@ -230,9 +254,13 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
uint32_t mdr_read(void);
void mdr_write(uint32_t value);
void mea_write(uint32_t reg_address);
+uint32_t port_reg_read(uint8_t port, uint32_t offset);
+void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
uint32_t reg_host_bridge_unit_read(uint32_t reg_address);
uint32_t reg_legacy_gpio_read(uint32_t reg_address);
void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value);
+uint64_t reg_mtrr_read(uint32_t reg_address);
+void reg_mtrr_write(uint32_t reg_address, uint64_t value);
uint32_t reg_rmu_temp_read(uint32_t reg_address);
#endif /* _QUARK_REG_ACCESS_H_ */
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
index 7472a3f..7e761ab 100644
--- a/src/soc/intel/quark/include/soc/romstage.h
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -26,8 +26,6 @@
#include <soc/reg_access.h>
asmlinkage void *car_stage_c_entry(void);
-uint32_t port_reg_read(uint8_t port, uint32_t offset);
-void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
void report_platform_info(void);
int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
void pcie_init(void);
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index edf67fe..7532039 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -154,6 +154,93 @@ void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value)
outl(value, get_legacy_gpio_address(reg_address));
}
+static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
+{
+ uint32_t offset;
+
+ /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */
+ if (index == MTRR_CAP_MSR)
+ offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
+ else if (index == MTRR_DEF_TYPE_MSR)
+ offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE;
+ else if (index == MTRR_FIX_64K_00000)
+ offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000;
+ else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000))
+ offset = ((index - MTRR_FIX_16K_80000) << 1)
+ + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000;
+ else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000))
+ offset = ((index - MTRR_FIX_4K_C0000) << 1)
+ + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
+ else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7)))
+ offset = (index - MTRR_PHYS_BASE(0))
+ + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
+ else {
+ printk(BIOS_DEBUG, "index: 0x%08lx\n", index);
+ die("Invalid MTRR index specified!\n");
+ }
+ return offset;
+}
+
+uint32_t port_reg_read(uint8_t port, uint32_t offset)
+{
+ /* Read the port register */
+ mea_write(offset);
+ mcr_write(QUARK_OPCODE_READ, port, offset);
+ return mdr_read();
+}
+
+void port_reg_write(uint8_t port, uint32_t offset, uint32_t value)
+{
+ /* Write the port register */
+ mea_write(offset);
+ mdr_write(value);
+ mcr_write(QUARK_OPCODE_WRITE, port, offset);
+}
+
+uint64_t reg_mtrr_read(uint32_t reg_address)
+{
+ uint32_t offset;
+ union {
+ uint64_t u64;
+ uint32_t u32[2];
+ } value;
+
+ /* Read the low 32-bits of the register */
+ offset = mtrr_index_to_host_bridge_register_offset(reg_address);
+ value.u64 = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
+
+ /* For 64-bit registers, read the upper 32-bits */
+ if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
+ && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
+ offset += 1;
+ value.u32[1] = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
+ offset);
+ }
+ return value.u64;
+}
+
+void reg_mtrr_write(uint32_t reg_address, uint64_t value)
+{
+ uint32_t offset;
+ union {
+ uint32_t u32[2];
+ uint64_t u64;
+ } msr;
+
+ /* Write the low 32-bits of the register */
+ msr.u64 = value;
+ offset = mtrr_index_to_host_bridge_register_offset(reg_address);
+ port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, msr.u32[0]);
+
+ /* For 64-bit registers, write the upper 32-bits */
+ if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
+ && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
+ offset += 1;
+ port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset,
+ msr.u32[1]);
+ }
+}
+
static uint32_t reg_pcie_afe_read(uint32_t reg_address)
{
/* Read the PCIE AFE register */
@@ -257,6 +344,11 @@ static uint64_t reg_read(struct reg_script_context *ctx)
value = reg_legacy_gpio_read(step->reg);
break;
+ case MTRR_REGS:
+ ctx->display_prefix = "MTRR";
+ value = reg_mtrr_read(step->reg);
+ break;
+
case PCIE_AFE_REGS:
ctx->display_prefix = "PCIe AFE";
value = reg_pcie_afe_read(step->reg);
@@ -312,6 +404,11 @@ static void reg_write(struct reg_script_context *ctx)
reg_legacy_gpio_write(step->reg, (uint32_t)step->value);
break;
+ case MTRR_REGS:
+ ctx->display_prefix = "MTRR";
+ reg_mtrr_write(step->reg, step->value);
+ break;
+
case PCIE_AFE_REGS:
ctx->display_prefix = "PCIe AFE";
reg_pcie_afe_write(step->reg, (uint32_t)step->value);
@@ -352,6 +449,28 @@ static void reg_write(struct reg_script_context *ctx)
}
}
+msr_t soc_mtrr_read(unsigned long index)
+{
+ union {
+ uint64_t u64;
+ msr_t msr;
+ } value;
+
+ value.u64 = reg_mtrr_read(index);
+ return value.msr;
+}
+
+void soc_mtrr_write(unsigned long index, msr_t msr)
+{
+ union {
+ uint64_t u64;
+ msr_t msr;
+ } value;
+
+ value.msr = msr;
+ reg_mtrr_write(index, value.u64);
+}
+
const struct reg_script_bus_entry soc_reg_script_bus_table = {
SOC_TYPE, reg_read, reg_write
};
diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c
index f03be1d..a18c27c 100644
--- a/src/soc/intel/quark/romstage/mtrr.c
+++ b/src/soc/intel/quark/romstage/mtrr.c
@@ -14,99 +14,7 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <soc/intel/common/util.h>
-#include <soc/pci_devs.h>
-#include <soc/romstage.h>
-
-static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
-{
- uint32_t offset;
-
- /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */
- if (index == MTRR_CAP_MSR)
- offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
- else if (index == MTRR_DEF_TYPE_MSR)
- offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE;
- else if (index == MTRR_FIX_64K_00000)
- offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000;
- else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000))
- offset = ((index - MTRR_FIX_16K_80000) << 1)
- + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000;
- else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000))
- offset = ((index - MTRR_FIX_4K_C0000) << 1)
- + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
- else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7)))
- offset = (index - MTRR_PHYS_BASE(0))
- + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
- else {
- printk(BIOS_DEBUG, "index: 0x%08lx\n", index);
- die("Invalid MTRR index specified!\n");
- }
- return offset;
-}
-
-uint32_t port_reg_read(uint8_t port, uint32_t offset)
-{
- /* Read the port register */
- mea_write(offset);
- mcr_write(QUARK_OPCODE_READ, port, offset);
- return mdr_read();
-}
-
-void port_reg_write(uint8_t port, uint32_t offset, uint32_t value)
-{
- /* Write the port register */
- mea_write(offset);
- mdr_write(value);
- mcr_write(QUARK_OPCODE_WRITE, port, offset);
-}
-
-msr_t soc_mtrr_read(unsigned long index)
-{
- uint32_t offset;
- union {
- uint64_t u64;
- msr_t msr;
- } value;
-
- /* Read the low 32-bits of the register */
- offset = mtrr_index_to_host_bridge_register_offset(index);
- value.u64 = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
-
- /* For 64-bit registers, read the upper 32-bits */
- if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
- && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
- offset += 1;
- value.u64 |= port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
- offset);
- }
- return value.msr;
-}
-
-void soc_mtrr_write(unsigned long index, msr_t msr)
-{
- uint32_t offset;
- union {
- uint32_t u32[2];
- msr_t msr;
- } value;
-
- /* Write the low 32-bits of the register */
- value.msr = msr;
- offset = mtrr_index_to_host_bridge_register_offset(index);
- port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, value.u32[0]);
-
- /* For 64-bit registers, write the upper 32-bits */
- if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
- && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
- offset += 1;
- port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset,
- value.u32[1]);
- }
-}
+#include <soc/reg_access.h>
asmlinkage void *soc_set_mtrrs(void *top_of_stack)
{
@@ -148,9 +56,8 @@ asmlinkage void *soc_set_mtrrs(void *top_of_stack)
mtrr_reg = MTRR_PHYS_BASE(0);
mtrr_data = top_of_stack;
mtrr_count = (*mtrr_data++) * 2;
- data.u64 = 0;
while (mtrr_count-- > 0)
- soc_mtrr_write(mtrr_reg++, data.msr);
+ reg_mtrr_write(mtrr_reg++, 0);
/* Setup the specified variable MTRRs */
mtrr_reg = MTRR_PHYS_BASE(0);
@@ -171,14 +78,10 @@ asmlinkage void *soc_set_mtrrs(void *top_of_stack)
asmlinkage void soc_enable_mtrrs(void)
{
- union {
- uint32_t u32[2];
- uint64_t u64;
- msr_t msr;
- } data;
+ uint64_t data;
/* Enable MTRR. */
- data.msr = soc_mtrr_read(MTRR_DEF_TYPE_MSR);
- data.u32[0] |= MTRR_DEF_TYPE_EN;
- soc_mtrr_write(MTRR_DEF_TYPE_MSR, data.msr);
+ data = reg_mtrr_read(MTRR_DEF_TYPE_MSR);
+ data |= MTRR_DEF_TYPE_EN;
+ reg_mtrr_write(MTRR_DEF_TYPE_MSR, data);
}
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