[coreboot-gerrit] New patch to review for coreboot: drivers/intel/fsp2_0: Add UPD display support
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Mon Jul 25 21:39:20 CEST 2016
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15847
-gerrit
commit d23cc3ff64c25c231abf684296fb92f81bb89bf4
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Thu Jul 21 09:48:49 2016 -0700
drivers/intel/fsp2_0: Add UPD display support
Add UPD display support:
* Add a Kconfig value to enable UPD value display
* Add a routine to display a UPD value
* Add calls in MemoryInit to conditionally display the UPD parameters
* Add a routine to display the architectural parameters for MemoryInit
* Add a weak routine to display the other UPD parameters for MemoryInit
* Add a call in SiliconInit to display the UPD parameters
* Add a weak routine to display the UPD parameters for SiliconInit
TEST=Build and run on Galileo Gen2.
Change-Id: I35fb8410c0bccf217b32af4b8bbe5ad6671f81f6
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/drivers/intel/fsp2_0/Kconfig | 22 +++++++++++++
src/drivers/intel/fsp2_0/include/fsp/api.h | 10 +++++-
src/drivers/intel/fsp2_0/include/fsp/util.h | 6 +++-
src/drivers/intel/fsp2_0/memory_init.c | 42 ++++++++++++++++++++++++-
src/drivers/intel/fsp2_0/silicon_init.c | 17 +++++++++-
src/drivers/intel/fsp2_0/util.c | 48 ++++++++++++++++++++++++++++-
6 files changed, 140 insertions(+), 5 deletions(-)
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 45679f7..8c45e73 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -1,3 +1,18 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015-2016 Intel Corp.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
config PLATFORM_USES_FSP2_0
bool
select UEFI_2_4_BINDING
@@ -12,6 +27,13 @@ config ADD_FSP_BINARIES
Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
use the FSP-T binary and it is not added.
+config DISPLAY_UPD_DATA
+ bool "Display UPD data"
+ default n
+ help
+ Display the user specified product data prior to memory
+ initialization.
+
config FSP_S_CBFS
string "Name of FSP-S in CBFS"
default "fsps.bin"
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 48cc54f..6026559 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -68,6 +68,14 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase);
void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd);
void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd);
+/* Callbacks for displaying UPD parameters */
+void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old,
+ const struct FSPM_ARCH_UPD *new);
+void fspm_display_upd_params(const struct FSPM_UPD *fspm_old_upd,
+ const struct FSPM_UPD *fspm_new_upd);
+void fsps_display_upd_params(const struct FSPS_UPD *fsps_old_upd,
+ const struct FSPS_UPD *fsps_new_upd);
+
/*
* # DOCUMENTATION:
*
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index 9f4d67a..63ef53e 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -53,4 +53,8 @@ void fsp_handle_reset(enum fsp_status status);
/* SoC/chipset must provide this to handle platform-specific reset codes */
void chipset_handle_reset(enum fsp_status status);
+/* Display UPD values */
+void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
+ uint64_t new);
+
#endif /* _FSP2_0_UTIL_H_ */
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index fb99244..9ec1951 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
* (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
* (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
*
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <lib.h>
#include <memrange.h>
#include <program_loading.h>
#include <reset.h>
@@ -209,6 +210,13 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
/* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd);
+ /* Display the UPD data */
+ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) {
+ fspm_display_arch_params(&upd->FspmArchUpd,
+ &fspm_upd.FspmArchUpd);
+ fspm_display_upd_params(upd, &fspm_upd);
+ }
+
/* Call FspMemoryInit */
fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit);
@@ -318,3 +326,35 @@ enum fsp_status fsp_memory_init(bool s3wake)
return do_fsp_memory_init(&hdr, s3wake, &memmap);
}
+
+void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old,
+ const struct FSPM_ARCH_UPD *new)
+{
+ /* Display the architectural parameters for MemoryInit */
+ printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n",
+ new);
+ fsp_display_upd_value("Revision", sizeof(old->Revision),
+ old->Revision, new->Revision);
+ fsp_display_upd_value("NvsBufferPtr", sizeof(old->NvsBufferPtr),
+ (uint64_t)(uintptr_t)old->NvsBufferPtr,
+ (uint64_t)(uintptr_t)new->NvsBufferPtr);
+ fsp_display_upd_value("StackBase", sizeof(old->StackBase),
+ (uint64_t)(uintptr_t)old->StackBase,
+ (uint64_t)(uintptr_t)new->StackBase);
+ fsp_display_upd_value("StackSize", sizeof(old->StackSize),
+ old->StackSize, new->StackSize);
+ fsp_display_upd_value("BootLoaderTolumSize",
+ sizeof(old->BootLoaderTolumSize),
+ old->BootLoaderTolumSize, new->BootLoaderTolumSize);
+ fsp_display_upd_value("BootMode", sizeof(old->BootMode),
+ old->BootMode, new->BootMode);
+}
+
+/* Display the UPD parameters for MemoryInit */
+__attribute__((weak)) void fspm_display_upd_params(
+ const struct FSPM_UPD *fspm_old_upd,
+ const struct FSPM_UPD *fspm_new_upd)
+{
+ printk(BIOS_DEBUG, "UPD values for MemoryInit:\n");
+ hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
+}
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index cc8c408..009e151 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
* (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <lib.h>
#include <program_loading.h>
#include <string.h>
#include <timestamp.h>
@@ -44,6 +45,11 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr)
/* Give SoC/mainboard a chance to populate entries */
platform_fsp_silicon_init_params_cb(&upd);
+ /* Display the UPD data */
+ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
+ fsps_display_upd_params(supd, &upd);
+
+ /* Call SiliconInit */
timestamp_add_now(TS_FSP_SILICON_INIT_START);
post_code(POST_FSP_SILICON_INIT);
silicon_init = (void *) (hdr->image_base +
@@ -104,3 +110,12 @@ enum fsp_status fsp_silicon_init(void)
return do_silicon_init(hdr);
}
+
+/* Display the UPD parameters for SiliconInit */
+__attribute__((weak)) void fsps_display_upd_params(
+ const struct FSPS_UPD *fsps_old_upd,
+ const struct FSPS_UPD *fsps_new_upd)
+{
+ printk(BIOS_DEBUG, "UPD values for SiliconInit:\n");
+ hexdump(fsps_new_upd, sizeof(*fsps_new_upd));
+}
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
index 1d3c744..3a0caa2 100644
--- a/src/drivers/intel/fsp2_0/util.c
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
* (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
*
@@ -166,3 +166,49 @@ void fsp_handle_reset(enum fsp_status status)
break;
}
}
+
+void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
+ uint64_t new)
+{
+ if (old == new) {
+ switch (size) {
+ case 1:
+ printk(BIOS_SPEW, " 0x%02llx: %s\n", new, name);
+ break;
+
+ case 2:
+ printk(BIOS_SPEW, " 0x%04llx: %s\n", new, name);
+ break;
+
+ case 4:
+ printk(BIOS_SPEW, " 0x%08llx: %s\n", new, name);
+ break;
+
+ case 8:
+ printk(BIOS_SPEW, " 0x%016llx: %s\n", new, name);
+ break;
+ }
+ } else {
+ switch (size) {
+ case 1:
+ printk(BIOS_SPEW, " 0x%02llx --> 0x%02llx: %s\n", old,
+ new, name);
+ break;
+
+ case 2:
+ printk(BIOS_SPEW, " 0x%04llx --> 0x%04llx: %s\n", old,
+ new, name);
+ break;
+
+ case 4:
+ printk(BIOS_SPEW, " 0x%08llx --> 0x%08llx: %s\n", old,
+ new, name);
+ break;
+
+ case 8:
+ printk(BIOS_SPEW, " 0x%016llx --> 0x%016llx: %s\n",
+ old, new, name);
+ break;
+ }
+ }
+}
More information about the coreboot-gerrit
mailing list