[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: ensure usb port 0 is in host mode

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15781

-gerrit

commit 568e9ff57844b011174ca969108e867fda33117d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 21 17:58:16 2016 -0500

    soc/intel/apollolake: ensure usb port 0 is in host mode
    
    The controller for device mode USB is not plan of record
    on apollolake. However, one still needs to configure the
    one port to be host mode by default such that the devices
    work as expected when plugged into the board.
    
    BUG=chrome-os-partner:54581,chrome-os-partner:54656
    TEST=Enabled xdci controller. Used USB type C->A dongle to
         check that a mass storage device worked on port 0 on
         reef.
    
    Change-Id: Ia9ec5076491f31bc5dc3d534e235fb49f7b2efac
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/apollolake/Makefile.inc          |   1 +
 src/soc/intel/apollolake/include/soc/pci_ids.h |   1 +
 src/soc/intel/apollolake/xhci.c                | 105 +++++++++++++++++++++++++
 3 files changed, 107 insertions(+)

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index fda3523..9e30df8 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -70,6 +70,7 @@ ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += smi.c
 ramstage-y += spi.c
+ramstage-y += xhci.c
 
 postcar-y += exit_car.S
 postcar-y += memmap.c
diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h
index 7c1a2b9..cd56fdd 100644
--- a/src/soc/intel/apollolake/include/soc/pci_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pci_ids.h
@@ -26,6 +26,7 @@
 #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI	0x5a96		/* 00:0d.2 */
 #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO		0x5a98		/* 00:0e.0 */
 #define PCI_DEVICE_ID_APOLLOLAKE_SATA		0x5ae0		/* 00:12.0 */
+#define PCI_DEVICE_ID_APOLLOLAKE_XHCI		0x5aa8		/* 00:15.0 */
 #define PCI_DEVICE_ID_APOLLOLAKE_I2C0		0x5aac		/* 00:16.0 */
 #define PCI_DEVICE_ID_APOLLOLAKE_I2C1		0x5aae		/* 00:16.1 */
 #define PCI_DEVICE_ID_APOLLOLAKE_I2C2		0x5ab0		/* 00:16.2 */
diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c
new file mode 100644
index 0000000..7b3cb46
--- /dev/null
+++ b/src/soc/intel/apollolake/xhci.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_devs.h>
+#include <soc/pci_ids.h>
+#include <timer.h>
+
+#define DUAL_ROLE_CFG0		0x80d8
+# define DRD_CONFIG_MASK	(0x3 << 0)
+# define DRD_CONFIG_DYNAMIC	(0x0 << 0)
+# define DRD_CONFIG_HOST	(0x1 << 0)
+# define DRD_CONFIG_DEVICE	(0x2 << 0)
+# define SW_VBUS_VALID_MASK	(1 << 24)
+# define SW_VBUS_DEASSERT_VALID	(0 << 24)
+# define SW_VBUS_ASSERT_VALID	(1 << 24)
+# define SW_IDPIN_EN_MASK	(1 << 21)
+# define SW_IDPIN_DIS		(0 << 21)
+# define SW_IDPIN_EN		(1 << 21)
+# define SW_IDPIN_MASK		(1 << 20)
+# define SW_IDPIN_HOST		(0 << 20)
+# define SW_IDPIN_DEVICE	(1 << 20)
+#define DUAL_ROLE_CFG1		0x80dc
+# define DRD_MODE_MASK		(1 << 29)
+# define DRD_MODE_DEVICE	(0 << 29)
+# define DRD_MODE_HOST		(1 << 29)
+
+static void configure_host_mode_port0(struct device *dev)
+{
+	uint32_t *cfg0;
+	uint32_t *cfg1;
+	const struct resource *res;
+	uint32_t reg;
+	struct device *xdci_dev = XDCI_DEV;
+	struct stopwatch sw;
+
+	/*
+	 * Only default to host mode if the xdci device is present and
+	 * enabled. If it's disabled assume the switch was already done
+	 * in FSP.
+	 */
+	if (xdci_dev == NULL || !xdci_dev->enabled)
+		return;
+
+	printk(BIOS_INFO, "Putting port 0 into host mode.\n");
+
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+
+	cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0);
+	cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1);
+
+	reg = read32(cfg0);
+	reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK);
+	reg &= ~(SW_VBUS_VALID_MASK);
+	reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST;
+	reg |= SW_VBUS_DEASSERT_VALID;
+	write32(cfg0, reg);
+
+	stopwatch_init_msecs_expire(&sw, 10);
+
+	/* Wait for the host mode status bit. */
+	while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) {
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_INFO, "Timed out waiting for host mode.\n");
+			break;
+		}
+	}
+
+	printk(BIOS_INFO, "XHCI port 0 host switch over took %lu ms\n",
+		stopwatch_duration_msecs(&sw));
+}
+
+static void xhci_init(struct device *dev)
+{
+	configure_host_mode_port0(dev);
+}
+
+static const struct device_operations device_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= xhci_init,
+};
+
+static const struct pci_driver pmc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_APOLLOLAKE_XHCI,
+};