[coreboot-gerrit] Patch set updated for coreboot: intel/lynxpoint, broadwell: Fix eDP display under Windows
Matt DeVillier (matt.devillier@gmail.com)
gerrit at coreboot.org
Sat Jul 23 09:12:01 CEST 2016
Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15261
-gerrit
commit 5eca9352de3117107193d47d45c58e4a5a8b1dcd
Author: Prabal Saha <coolstarorganization at gmail.com>
Date: Sat Jun 18 20:47:21 2016 -0700
intel/lynxpoint,broadwell: Fix eDP display under Windows
Without this patch, eDP output is non-functional under Windows
regardless of payload (SeaBIOS, Tianocore) or video init method
(VBIOS, GOP driver) when the standard Intel HD graphics driver is
loaded.
Test: Boot peppy and auron_paine to Windows with functional display
in SeaBIOS. Install Intel HD Graphics driver with full video
acceleration and internal display functional.
Debugging method: adjust location of call to run VBIOS within
coreboot, observed that eDP output functional if the VBIOS is run
before the power optimizer lines, broken if run afterwardss.
Change-Id: I6d8252e3de396887c84533e355f41693b9ea7514
Signed-off-by: Prabal Saha <coolstarorganization at gmail.com>
---
src/soc/intel/broadwell/Kconfig | 9 +++++++++
src/soc/intel/broadwell/lpc.c | 2 ++
src/southbridge/intel/lynxpoint/Kconfig | 9 +++++++++
src/southbridge/intel/lynxpoint/lpc.c | 2 ++
4 files changed, 22 insertions(+)
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 1c29d77..7c92284 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -214,4 +214,13 @@ config CHIPSET_BOOTBLOCK_INCLUDE
string
default "soc/intel/broadwell/bootblock/timestamp.inc"
+config BROADWELL_POWER_OPTIMIZER
+ bool "Enable Power Optimizer"
+ default y if CHROMEOS
+ help
+ Enable the power optimizer for the High Speed I/O
+ Power Control (HSIOPC). This can break graphics
+ under Windows, but can improve battery life under
+ 'mostly idle' conditions.
+
endif
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 7e57b23..231399b 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -283,6 +283,7 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
+#if IS_ENABLED(CONFIG_BROADWELL_POWER_OPTIMIZER)
/* Power Optimizer */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
@@ -294,6 +295,7 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000),
+#endif
REG_SCRIPT_END
};
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 744a31e..775e9f3 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -95,4 +95,13 @@ config LOCK_MANAGEMENT_ENGINE
bool
default n
+config LYNXPOINT_POWER_OPTIMIZER
+ bool "Enable Power Optimizer"
+ default y if CHROMEOS
+ help
+ Enable the power optimizer for the High Speed I/O
+ Power Control (HSIOPC). This can break graphics
+ under Windows, but can improve battery life under
+ 'mostly idle' conditions.
+
endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f4c3826..1d20bbb 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -346,6 +346,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x33b4, 0, 0x00007001),
RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff),
RCBA_RMW_REG_32(0x3354, 0, 0x00000001),
+#if IS_ENABLED(CONFIG_LYNXPOINT_POWER_OPTIMIZER)
RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */
RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */
@@ -353,6 +354,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */
RCBA_RMW_REG_32(0x3a80, 0, 0x05145005),
+#endif
RCBA_END_CONFIG
};
More information about the coreboot-gerrit
mailing list