[coreboot-gerrit] Patch set updated for coreboot: intel post-car: Separate files for setup_romstage_after_car()
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Fri Jul 22 15:49:53 CEST 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15762
-gerrit
commit 2c3b2ab9392ae2275560aad2607057f6aa86e247
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Mon Jun 27 13:24:11 2016 +0300
intel post-car: Separate files for setup_romstage_after_car()
Have a common romstage.c file to prepare CAR stack guards.
Have a postcar.c file for each cache_as_ram.inc to keep
future MTRR changes more manageable.
Move old sockets to use romstage_legacy.c. These will not be
converted to RELOCATABLE_RAMSTAGE as boards are candidates for
getting dropped from the tree anyways.
Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/car/postcar.c | 21 +++++++++++++
src/cpu/intel/car/romstage.c | 47 ++++++++++++++++++++++++++++-
src/cpu/intel/car/romstage_legacy.c | 20 ++++++++++++
src/cpu/intel/model_2065x/Makefile.inc | 1 +
src/cpu/intel/model_2065x/postcar.c | 21 +++++++++++++
src/cpu/intel/model_206ax/Makefile.inc | 1 +
src/cpu/intel/model_206ax/postcar.c | 21 +++++++++++++
src/cpu/intel/model_6ex/postcar.c | 21 +++++++++++++
src/cpu/intel/slot_1/Makefile.inc | 2 +-
src/cpu/intel/socket_441/Makefile.inc | 1 +
src/cpu/intel/socket_BGA956/Makefile.inc | 1 +
src/cpu/intel/socket_FCBGA559/Makefile.inc | 1 +
src/cpu/intel/socket_FC_PGA370/Makefile.inc | 2 +-
src/cpu/intel/socket_LGA771/Makefile.inc | 1 +
src/cpu/intel/socket_LGA775/Makefile.inc | 2 +-
src/cpu/intel/socket_PGA370/Makefile.inc | 2 +-
src/cpu/intel/socket_mFCBGA479/Makefile.inc | 2 +-
src/cpu/intel/socket_mFCPGA478/Makefile.inc | 1 +
src/cpu/intel/socket_mPGA479M/Makefile.inc | 2 +-
src/cpu/intel/socket_mPGA604/Makefile.inc | 1 +
src/include/cpu/intel/romstage.h | 23 ++++++++++++++
21 files changed, 187 insertions(+), 7 deletions(-)
diff --git a/src/cpu/intel/car/postcar.c b/src/cpu/intel/car/postcar.c
new file mode 100644
index 0000000..062a509
--- /dev/null
+++ b/src/cpu/intel/car/postcar.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 ChromeOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/romstage.h>
+
+void *setup_romstage_stack_after_car(void)
+{
+ return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index c6df446..0cf4ed47 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -1,7 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <program_loading.h>
void * asmlinkage romstage_main(unsigned long bist)
{
+ int i;
+ void *romstage_stack_after_car;
+ const int num_guards = 4;
+ const u32 stack_guard = 0xdeadbeef;
+ u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
+ CONFIG_DCACHE_RAM_SIZE -
+ CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
+
+ printk(BIOS_DEBUG, "Setting up stack guards.\n");
+ for (i = 0; i < num_guards; i++)
+ stack_base[i] = stack_guard;
+
mainboard_romstage_entry(bist);
- return (void*)CONFIG_RAMTOP;
+
+ /* Check the stack. */
+ for (i = 0; i < num_guards; i++) {
+ if (stack_base[i] == stack_guard)
+ continue;
+ printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
+ }
+
+ /* Get the stack to use after cache-as-ram is torn down. */
+ romstage_stack_after_car = setup_romstage_stack_after_car();
+
+ return romstage_stack_after_car;
+}
+
+void asmlinkage romstage_after_car(void)
+{
+ /* Load the ramstage. */
+ run_ramstage();
}
diff --git a/src/cpu/intel/car/romstage_legacy.c b/src/cpu/intel/car/romstage_legacy.c
new file mode 100644
index 0000000..560cd7a
--- /dev/null
+++ b/src/cpu/intel/car/romstage_legacy.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/romstage.h>
+
+void * asmlinkage romstage_main(unsigned long bist)
+{
+ mainboard_romstage_entry(bist);
+ return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index cdf9fed..4c6af41 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -20,4 +20,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
+romstage-y += postcar.c
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/model_2065x/postcar.c b/src/cpu/intel/model_2065x/postcar.c
new file mode 100644
index 0000000..062a509
--- /dev/null
+++ b/src/cpu/intel/model_2065x/postcar.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 ChromeOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/romstage.h>
+
+void *setup_romstage_stack_after_car(void)
+{
+ return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 25f0742..adce57c 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -10,4 +10,5 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
+romstage-y += postcar.c
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/model_206ax/postcar.c b/src/cpu/intel/model_206ax/postcar.c
new file mode 100644
index 0000000..062a509
--- /dev/null
+++ b/src/cpu/intel/model_206ax/postcar.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 ChromeOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/romstage.h>
+
+void *setup_romstage_stack_after_car(void)
+{
+ return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/cpu/intel/model_6ex/postcar.c b/src/cpu/intel/model_6ex/postcar.c
new file mode 100644
index 0000000..062a509
--- /dev/null
+++ b/src/cpu/intel/model_6ex/postcar.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 ChromeOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/romstage.h>
+
+void *setup_romstage_stack_after_car(void)
+{
+ return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
index 512571d..ca7c154 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -29,4 +29,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc
index dbf300b..a11b1cd 100644
--- a/src/cpu/intel/socket_441/Makefile.inc
+++ b/src/cpu/intel/socket_441/Makefile.inc
@@ -10,3 +10,4 @@ subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c
+romstage-y += ../car/postcar.c
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index 22c1a7c..d6e9619 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -10,4 +10,5 @@ subdirs-y += ../speedstep
# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../model_6ex/postcar.c
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
index 082c472..e3fce4a 100644
--- a/src/cpu/intel/socket_FCBGA559/Makefile.inc
+++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -9,3 +9,4 @@ subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c
+romstage-y += ../car/postcar.c
diff --git a/src/cpu/intel/socket_FC_PGA370/Makefile.inc b/src/cpu/intel/socket_FC_PGA370/Makefile.inc
index cc6e299..c06082c 100644
--- a/src/cpu/intel/socket_FC_PGA370/Makefile.inc
+++ b/src/cpu/intel/socket_FC_PGA370/Makefile.inc
@@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc
index d0a5b63..b9dd70b 100644
--- a/src/cpu/intel/socket_LGA771/Makefile.inc
+++ b/src/cpu/intel/socket_LGA771/Makefile.inc
@@ -9,4 +9,5 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../model_6ex/postcar.c
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index 371a801..a64d8f1 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -16,4 +16,4 @@ subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c
-romstage-y += ../car/romstage.c
+romstage-y += ../car/postcar.c
diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc
index d0f5405..9265ba4 100644
--- a/src/cpu/intel/socket_PGA370/Makefile.inc
+++ b/src/cpu/intel/socket_PGA370/Makefile.inc
@@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
index c846598..918a54e 100644
--- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc
+++ b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
@@ -7,4 +7,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
index 6056d3c..943d441 100644
--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc
+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
@@ -12,4 +12,5 @@ subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../model_6ex/postcar.c
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc
index 2a3187a..c35ca46 100644
--- a/src/cpu/intel/socket_mPGA479M/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA479M/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc
index 98306d4..90d6eff 100644
--- a/src/cpu/intel/socket_mPGA604/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA604/Makefile.inc
@@ -10,4 +10,5 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+romstage-y += ../car/postcar.c
romstage-y += ../car/romstage.c
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index d443564..07e2b9d 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -4,6 +4,29 @@
#include <arch/cpu.h>
void mainboard_romstage_entry(unsigned long bist);
+
+/* romstage_main is called from the cache-as-ram assembly file. The return
+ * value is the stack value to be used for romstage once cache-as-ram is
+ * torn down. The following values are pushed onto the stack to setup the
+ * MTRRs:
+ * +0: Number of MTRRs
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
+ * ...
+ */
+void *setup_romstage_stack_after_car(void);
+
+/* romstage_main is called from the cache-as-ram assembly file to prepare
+ * CAR stack guards.*/
void * asmlinkage romstage_main(unsigned long bist);
+/* romstage_after_car() is the C function called after cache-as-ram has
+ * been torn down. It is responsible for loading the ramstage. */
+void asmlinkage romstage_after_car(void);
#endif /* _CPU_INTEL_ROMSTAGE_H */
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