[coreboot-gerrit] New patch to review for coreboot: intel car: Use MTRR WRPROT type for XIP cache

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15778

-gerrit

commit 9f2c9144806c5aa843ca8379e03a9d7512cbb482
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Jul 21 19:51:01 2016 +0300

    intel car: Use MTRR WRPROT type for XIP cache
    
    XIP cachelines contain the executable to run, we never want
    that to get modified. With the change such erronous writes
    are ignored and next cacheline miss will fetch from boot
    media (SPI / FWH flash).
    
    Change-Id: I52b62866b5658e103281ffa1a91e1c64262f3175
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/car/cache_as_ram_ht.inc    | 2 +-
 src/cpu/intel/model_6ex/cache_as_ram.inc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index f9a2b36..0ec2a9d 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -310,7 +310,7 @@ no_msr_11e:
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
-	orl	$MTRR_TYPE_WRBACK, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 
 	movl	$MTRR_PHYS_MASK(1), %ecx
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 1f2445a..b4c8d62 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -111,7 +111,7 @@ clear_mtrrs:
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
-	orl	$MTRR_TYPE_WRBACK, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 
 	movl	$MTRR_PHYS_MASK(1), %ecx