[coreboot-gerrit] New patch to review for coreboot: intel/amenia: GPIO changes for PMIC and LTB in S3/S0ix

[Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com)]

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15777

-gerrit

commit 5225a5308bc683439e44113299d944437cb59fd5
Author: Shankar, Vaibhav <vaibhav.shankar at intel.com>
Date:   Mon Jul 18 12:07:34 2016 -0700

    intel/amenia: GPIO changes for PMIC and LTB in S3/S0ix
    
    LTB:Setting the iosstate for the JTAG GPIO's to access the SoC registers
    when the system is in S3/S0ix.
    PMIC:Setting iosstate for the I2C lines to assert the SLP_S0 signal.
    
    BUG=SYSCROS-14672
    TEST=suspend the system to S3/S0ix and read any soc registers using LTB.
    
    Change-Id: Iec2dd659ea21f07d0bfe74194756786375cf775c
    Signed-off-by: venkateswarlu vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
 src/mainboard/intel/amenia/gpio.h | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h
index a3b7611..230c155 100644
--- a/src/mainboard/intel/amenia/gpio.h
+++ b/src/mainboard/intel/amenia/gpio.h
@@ -120,7 +120,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */
 	PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */
 	PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1),	/* PMU_RSTBTN_N */
-	PAD_CFG_NF(PMU_SLP_S0_B, NONE, DEEP, NF1), /* PMU_SLP_S0_N */
+	PAD_CFG_NF_IOSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IOSTANDBY),   /* PMU_SLP_S0_N */
 	PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */
 	PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */
 	PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */
@@ -164,7 +164,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(PMC_SPI_CLK, DN_20K), /* PMC_SPI_CLK */
 	/* PMIC */
 	PAD_NC(PMIC_PWRGOOD, NONE), /* PMIC_PWRGOOD */
-	PAD_NC(PMIC_RESET_B, NONE), /* PMIC_RESET_B */
+	PAD_CFG_NF_IOSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IOSTANDBY),  /* PMIC_RESET_B */
 	PAD_NC(GPIO_213, NONE), /* PMIC_SDWN_B */
 	PAD_NC(GPIO_214, DN_20K), /* PMIC_BCUDISW2 */
 	PAD_NC(GPIO_215, DN_20K), /* PMIC_BCUDISCRIT */
@@ -298,6 +298,13 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPIO_71, DN_20K), /* GP_CAMERASB09 */
 	PAD_NC(GPIO_72, DN_20K), /* GP_CAMERASB10 */
 	PAD_NC(GPIO_73, DN_20K), /* GP_CAMERASB11 */
+        /*JTAG*/
+        PAD_CFG_NF_JTAG_IOSTATE(TCK, DN_20K,DEEP,NF1 , IOSTANDBY),
+        PAD_CFG_NF_JTAG_IOSTATE(TRST_B, DN_20K, DEEP, NF1, IOSTANDBY),
+        PAD_CFG_NF_JTAG_IOSTATE(TMS, UP_20K, DEEP, NF1, IOSTANDBY),
+        PAD_CFG_NF_JTAG_IOSTATE(TDI, UP_20K, DEEP, NF1, IOSTANDBY),
+        PAD_CFG_NF_JTAG_TDO_IOSTATE(TDO, UP_20K, DEEP, NF1, IOSTANDBY),
+
 	/** End of North Community */
 };