[coreboot-gerrit] New patch to review for coreboot: intel post-car: Separate files for romstage_main_entry()

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Wed Jul 20 15:09:13 CEST 2016 

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15762

-gerrit

commit 613824ce78430ea4e27d1fd3244135dd97296f96
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Jun 27 13:24:11 2016 +0300

    intel post-car: Separate files for romstage_main_entry()
    
    Have a romstage.c file for each cache_as_ram.inc to keep
    coming MTRR changes more manageable.
    
    Move old sockets to use romstage_legacy.c. These will not be
    converted to RELOCATABLE_RAMSTAGE as boards are candidates for
    getting dropped from the tree anyways.
    
    Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/car/romstage.c                | 13 +++++++++++++
 src/cpu/intel/car/romstage_legacy.c         | 20 ++++++++++++++++++++
 src/cpu/intel/model_2065x/Makefile.inc      |  2 +-
 src/cpu/intel/model_2065x/romstage.c        | 20 ++++++++++++++++++++
 src/cpu/intel/model_206ax/Makefile.inc      |  2 +-
 src/cpu/intel/model_206ax/romstage.c        | 20 ++++++++++++++++++++
 src/cpu/intel/model_6ex/romstage.c          | 20 ++++++++++++++++++++
 src/cpu/intel/slot_1/Makefile.inc           |  2 +-
 src/cpu/intel/socket_BGA956/Makefile.inc    |  2 +-
 src/cpu/intel/socket_FC_PGA370/Makefile.inc |  2 +-
 src/cpu/intel/socket_LGA771/Makefile.inc    |  2 +-
 src/cpu/intel/socket_LGA775/Makefile.inc    |  1 -
 src/cpu/intel/socket_PGA370/Makefile.inc    |  2 +-
 src/cpu/intel/socket_mFCBGA479/Makefile.inc |  2 +-
 src/cpu/intel/socket_mFCPGA478/Makefile.inc |  2 +-
 src/cpu/intel/socket_mPGA479M/Makefile.inc  |  2 +-
 16 files changed, 103 insertions(+), 11 deletions(-)

diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index c6df446..560cd7a 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
 #include <cpu/intel/romstage.h>
 
 void * asmlinkage romstage_main(unsigned long bist)
diff --git a/src/cpu/intel/car/romstage_legacy.c b/src/cpu/intel/car/romstage_legacy.c
new file mode 100644
index 0000000..560cd7a
--- /dev/null
+++ b/src/cpu/intel/car/romstage_legacy.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/romstage.h>
+
+void * asmlinkage romstage_main(unsigned long bist)
+{
+	mainboard_romstage_entry(bist);
+	return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index cdf9fed..43927a8 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -20,4 +20,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += romstage.c
diff --git a/src/cpu/intel/model_2065x/romstage.c b/src/cpu/intel/model_2065x/romstage.c
new file mode 100644
index 0000000..560cd7a
--- /dev/null
+++ b/src/cpu/intel/model_2065x/romstage.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/romstage.h>
+
+void * asmlinkage romstage_main(unsigned long bist)
+{
+	mainboard_romstage_entry(bist);
+	return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 25f0742..fbc65e2 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -10,4 +10,4 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += romstage.c
diff --git a/src/cpu/intel/model_206ax/romstage.c b/src/cpu/intel/model_206ax/romstage.c
new file mode 100644
index 0000000..560cd7a
--- /dev/null
+++ b/src/cpu/intel/model_206ax/romstage.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/romstage.h>
+
+void * asmlinkage romstage_main(unsigned long bist)
+{
+	mainboard_romstage_entry(bist);
+	return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/cpu/intel/model_6ex/romstage.c b/src/cpu/intel/model_6ex/romstage.c
new file mode 100644
index 0000000..560cd7a
--- /dev/null
+++ b/src/cpu/intel/model_6ex/romstage.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/romstage.h>
+
+void * asmlinkage romstage_main(unsigned long bist)
+{
+	mainboard_romstage_entry(bist);
+	return (void*)CONFIG_RAMTOP;
+}
diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
index 512571d..ca7c154 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -29,4 +29,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index 22c1a7c..b167d63 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../speedstep
 
 # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../model_6ex/romstage.c
diff --git a/src/cpu/intel/socket_FC_PGA370/Makefile.inc b/src/cpu/intel/socket_FC_PGA370/Makefile.inc
index cc6e299..c06082c 100644
--- a/src/cpu/intel/socket_FC_PGA370/Makefile.inc
+++ b/src/cpu/intel/socket_FC_PGA370/Makefile.inc
@@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc
index d0a5b63..5ddeed8 100644
--- a/src/cpu/intel/socket_LGA771/Makefile.inc
+++ b/src/cpu/intel/socket_LGA771/Makefile.inc
@@ -9,4 +9,4 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../model_6ex/romstage.c
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index 371a801..54a762e 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -16,4 +16,3 @@ subdirs-y += ../speedstep
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
 romstage-y += ../car/romstage.c
-romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc
index d0f5405..9265ba4 100644
--- a/src/cpu/intel/socket_PGA370/Makefile.inc
+++ b/src/cpu/intel/socket_PGA370/Makefile.inc
@@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
index c846598..918a54e 100644
--- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc
+++ b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
@@ -7,4 +7,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
index 6056d3c..f9ee695 100644
--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc
+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
@@ -12,4 +12,4 @@ subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../model_6ex/romstage.c
diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc
index 2a3187a..c35ca46 100644
--- a/src/cpu/intel/socket_mPGA479M/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA479M/Makefile.inc
@@ -10,4 +10,4 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage_legacy.c

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