[coreboot-gerrit] New patch to review for coreboot: intel car: Remove guard on XIP_ROM_SIZE

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15758

-gerrit

commit 4946582b61977be9d894d9a173b62e641afd99e3
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Jul 20 13:31:00 2016 +0300

    intel car: Remove guard on XIP_ROM_SIZE
    
    These guards have been removed starting with model_206ax.
    
    Change-Id: Id63034ec4080e37eee2c120aa1f1ef604db5b203
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/car/cache_as_ram.inc       | 3 ---
 src/cpu/intel/car/cache_as_ram_ht.inc    | 2 --
 src/cpu/intel/model_6ex/cache_as_ram.inc | 2 --
 3 files changed, 7 deletions(-)

diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 3d7be8b..442c2b4 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -225,8 +225,6 @@ clear_fixed_var_mtrr_out:
 	simplemask CacheSize, 0
 	wrmsr
 
-#if CONFIG_XIP_ROM_SIZE
-
 	/*
 	 * Enable write base caching so we can do execute in place (XIP)
 	 * on the flash ROM.
@@ -246,7 +244,6 @@ clear_fixed_var_mtrr_out:
 	movl	$0x0000000f, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
 
 	/* Enable cache. */
 	movl	%cr0, %eax
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 095b9b6..84a55c7 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -302,7 +302,6 @@ no_msr_11e:
 
 	post_code(0x2d)
 
-#if CONFIG_XIP_ROM_SIZE
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
@@ -319,7 +318,6 @@ no_msr_11e:
 	rdmsr
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
 
 	/* Enable cache. */
 	movl	%cr0, %eax
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 6b80e7a..edd9e6c 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -96,7 +96,6 @@ clear_mtrrs:
 	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
-#if CONFIG_XIP_ROM_SIZE
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
@@ -113,7 +112,6 @@ clear_mtrrs:
 	movl	$CPU_PHYSMASK_HI, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
 
 	/* Enable cache. */
 	movl	%cr0, %eax