[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Correct the gpio bank irq

[Jagadish Krishnamoorthy (jagadish.krishnamoorthy@intel.com)]

Jagadish Krishnamoorthy (jagadish.krishnamoorthy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15756

-gerrit

commit c270d86fd3e6d8d4cab0b125f9f51392fe49d544
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date:   Tue Jul 19 16:25:12 2016 -0700

    soc/intel/apollolake: Correct the gpio bank irq
    
    The gpio bank irq is not correct and hence gpio
    bank handler is never called in case of gpio based irq.
    Correct the gpio bank irq to enable gpio based irq.
    
    BUG=chrome-os-partner:55433
    TEST=cat /proc/interrupts | grep INT3452 should
    output 14.
    
    Change-Id: I54253786425b7d4c2007043d49a91dfa6db0397b
    Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
---
 src/soc/intel/apollolake/acpi/soc_int.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl
index c7259d0..c643244 100644
--- a/src/soc/intel/apollolake/acpi/soc_int.asl
+++ b/src/soc/intel/apollolake/acpi/soc_int.asl
@@ -24,7 +24,7 @@
 #define UART2_INT	6	/* Need to be shared by PMC and SCC only*/
 #define UART3_INT	7	/* Need to be shared by PMC and SCC only*/
 #define XDCI_INT	13	/* Need to be shared by PMC and SCC only*/
-#define GPIO_BANK_INT	16
+#define GPIO_BANK_INT	14
 #define NPK_INT		16
 #define PIRQA_INT	16
 #define PIRQB_INT	17