[coreboot-gerrit] New patch to review for coreboot: timestamp: Drop duplicate TS_END_ROMSTAGE entries

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Wed Jul 20 06:28:54 CEST 2016


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15755

-gerrit

commit fc993cf603b03e9fe897d26275b6dc0ae1aa8399
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Jul 20 07:20:50 2016 +0300

    timestamp: Drop duplicate TS_END_ROMSTAGE entries
    
    This entry gets added in run_ramstage().
    
    Change-Id: I18cda4ead3614c6d07c3269cbee53e6def6408c7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/mainboard/asus/kcma-d8/romstage.c      | 2 --
 src/mainboard/asus/kgpe-d16/romstage.c     | 2 --
 src/southbridge/intel/fsp_i89xx/romstage.c | 2 --
 3 files changed, 6 deletions(-)

diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index cf0ab39..3f96c52 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -588,8 +588,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
 	pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 8825b23..fd3411a 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -629,8 +629,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
 	pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index 5bcc8fa..f20d73d 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -212,8 +212,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	*(uint32_t*)cbmem_hob_ptr = (uint32_t)HobListPtr;
 	post_code(0x4f);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
 



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