[coreboot-gerrit] New patch to review for coreboot: mainboard/google/reef: reverse the memory config bits

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15753

-gerrit

commit 5005a646f36e7b79b53f312eaee27b40132e1a39
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Jul 19 17:39:05 2016 -0500

    mainboard/google/reef: reverse the memory config bits
    
    I mistakenly assumed the order of the bits matched how one
    would assign values as they wrote them msb .. lsb. However, the
    gpio lib doesn't do that. Correct the order so that values are
    read out correctly.
    
    BUG=chrome-os-partner:54949
    
    Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/reef/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index 2c68b60..e641a97 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -112,7 +112,7 @@ static const struct lpddr4_cfg lp4cfg = {
 void mainboard_memory_init_params(struct FSPM_UPD *memupd)
 {
 	int mem_sku;
-	gpio_t pads[] = { MEM_CONFIG3, MEM_CONFIG2, MEM_CONFIG1, MEM_CONFIG0 };
+	gpio_t pads[] = { MEM_CONFIG0, MEM_CONFIG1, MEM_CONFIG2, MEM_CONFIG3 };
 
 	/*
 	 * Read memory SKU id with internal pullups enabled to handle