[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: add offset of GPIO_TIER1_SCI_EN bit

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 0cf11cb7837d34589da466dcdcfa0aecc1e6c3db
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Mon Jul 11 16:03:52 2016 -0700

    soc/intel/apollolake: add offset of GPIO_TIER1_SCI_EN bit
    
    This patch adds the support for gpio_tier1_sci_en bit which
    needs to be set before going to sleep so that when
    gpio_tier1_sci_sts bit gets set platform can wake
    from S3.
    
    BUG = chrome-os-partner:53992
    TEST = Platform wakes from S3 on lidopen,key press.
           Tested on Amenia and Reef boards.
    
    Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
    Reviewed-on: https://review.coreboot.org/15612
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/15612 for details.

-gerrit