[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: work around FSP for gpio interrupt polarity

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 81d1e09113bc12ea9427e9522d4f5eab982c145e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Jul 13 01:49:10 2016 -0500

    soc/intel/apollolake: work around FSP for gpio interrupt polarity
    
    FSP is currently setting a hard-coded policy for the interrupt
    polarity settings. When the mainboard has already set the GPIO
    settings up prior to SiliconInit being called that results
    in the previous settings being dropped. Work around FSP's
    default policy until FSP is fixed.
    
    BUG=chrome-os-partner:54955
    
    Change-Id: Ibbd8c4894d8fbce479aeb73aa775b67df15dae85
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/15649
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>
    Reviewed-by: Furquan Shaikh <furquan at google.com>


See https://review.coreboot.org/15649 for details.

-gerrit