[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Add handler for SCI

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 7f149c7bb4744459c775c32c71fe222c792cea19
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Thu Jul 7 14:48:21 2016 -0700

    soc/intel/apollolake: Add handler for SCI
    
    This patch adds the handler to enable bit for gpio_tier1_sci_en.
    gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS
    bit to generate a wake event and/or an SCI or SMI#. We are setting
    the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit
    if set from BIOS. As per ACPI spec _GPE is defined as the Named
    Object  that evaluates to either an integer or a package. If _GPE
    evaluates to an integer, the value is the bit assignment of the SCI
    interrupt within the GPEx_STS register of a GPE block described in
    the FADT that the embedded controller will trigger. FADT right now
    has no mechanism to acheive the same.
    
    Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
    Reviewed-on: https://review.coreboot.org/15578
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15578 for details.

-gerrit