[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Add GPE routing code

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 5b6c5a500ed416f033a22eed1d8174063ebaf143
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Tue Jun 7 02:06:28 2016 -0700

    soc/intel/apollolake: Add GPE routing code
    
    This patch adds the basic framework for SCI to GPE routing code.
    
    BUG = chrome-os-partner:53438
    TEST = Toogle pch_sci_l from ec console using gpioset command and
    	see that the sci counter increases in /sys/firmware/acpi/interrupt
    	and also 9 in /proc/interrupts.
    
    Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
    Reviewed-on: https://review.coreboot.org/15324
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See https://review.coreboot.org/15324 for details.

-gerrit