[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15055

-gerrit

commit 1a41598ab662ec797c8a90b248ce3333af83a8cd
Author: Saurabh Satija <saurabh.satija at intel.com>
Date:   Tue May 3 15:15:31 2016 -0700

    soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree
    
    Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784
    Signed-off-by: Saurabh Satija <saurabh.satija at intel.com>
    Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
 src/soc/intel/apollolake/chip.c | 2 ++
 src/soc/intel/apollolake/chip.h | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 00470a2..ae9f09e 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -332,6 +332,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 
 	silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
 
+	silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
+
 	/* Disable setting of EISS bit in FSP. */
 	silconfig->SpiEiss = 0;
 }
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index aabd42d..fa79cf8 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -101,6 +101,9 @@ struct soc_intel_apollolake_config {
 	uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
 	uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
 	uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */
+
+	/* Configure LPSS S0ix Enable */
+	uint8_t lpss_s0ix_enable;
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */