[coreboot-gerrit] New patch to review for coreboot: soc/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13403

-gerrit

commit e2ea7793ad49411a87a2a51a8a3fa1e716e30c24
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date:   Thu Jan 7 16:54:39 2016 -0800

    soc/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds
    
    Add chromeos required gnvs feature, the gnvs table stays in both CBMEM
    and acpi dsdt tables.
    
    Change-Id: Id91e351ca7af06da6a9c89d2b353028323cded3c
    Signed-off-by: Zhao, Lijian <lijian.zhao at intel.com>
---
 src/soc/intel/apollolake/acpi.c             | 29 +++++++++++++++++++++++++++++
 src/soc/intel/apollolake/include/soc/acpi.h |  2 ++
 src/soc/intel/apollolake/include/soc/nvs.h  | 26 ++++++++++++++++++++++++++
 src/soc/intel/apollolake/lpc.c              |  7 +++++++
 4 files changed, 64 insertions(+)

diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 3b622b8..940b81b 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -11,12 +11,24 @@
  */
 
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
+#include <cbmem.h>
 #include <cpu/x86/smm.h>
 #include <soc/acpi.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
+static void acpi_create_gnvs(struct global_nvs_t *gnvs)
+{
+	if(IS_ENABLED(CONFIG_CHROMEOS)) {
+		/* Initialize Verified Boot data */
+		chromeos_init_vboot(&(gnvs->chromeos));
+		gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+	}
+}
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
@@ -120,3 +132,20 @@ unsigned long southbridge_write_acpi_tables(device_t device,
 {
 	return acpi_write_hpet(device, current, rsdp);
 }
+
+void southbridge_inject_dsdt(device_t device)
+{
+	struct global_nvs_t *gnvs;
+
+	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+
+	if (gnvs) {
+		acpi_create_gnvs(gnvs);
+		acpi_save_gnvs((unsigned long)gnvs);
+
+		/* Add it to DSDT.  */
+		acpigen_write_scope("\\");
+		acpigen_write_name_dword("NVSA", (uint32_t)gnvs);
+		acpigen_pop_len();
+	}
+}
diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h
index bb655eb..e629362 100644
--- a/src/soc/intel/apollolake/include/soc/acpi.h
+++ b/src/soc/intel/apollolake/include/soc/acpi.h
@@ -14,10 +14,12 @@
 #define _SOC_APOLLOLAKE_ACPI_H_
 
 #include <arch/acpi.h>
+#include <soc/nvs.h>
 
 /* Zero value won't be programmed again in FADT table. */
 void soc_fill_common_fadt(acpi_fadt_t * fadt);
 
+void southbridge_inject_dsdt(device_t device);
 unsigned long southbridge_write_acpi_tables(device_t device,
                 unsigned long current, struct acpi_rsdp *rsdp);
 
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
new file mode 100644
index 0000000..af7b546
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_NVS_H_
+#define _SOC_APOLLOLAKE_NVS_H_
+
+#include <vendorcode/google/chromeos/gnvs.h>
+
+struct global_nvs_t {
+	/* Miscellaneous */
+	uint8_t unused[256];
+
+	/* ChromeOS specific (0x100 - 0xfff) */
+	chromeos_acpi_t chromeos;
+} __attribute__((packed));
+
+#endif	/* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 120b0e9..07ac3f6 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -10,11 +10,13 @@
  * (at your option) any later version.
  */
 
+#include <cbmem.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <soc/acpi.h>
 #include <soc/pci_ids.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 static void soc_lpc_add_io_resources(device_t dev)
 {
@@ -29,17 +31,22 @@ static void soc_lpc_add_io_resources(device_t dev)
 
 static void soc_lpc_read_resources(device_t dev)
 {
+	struct global_nvs_t *gnvs;
 	/* Get the PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
 	/* Add IO resources to LPC. */
 	soc_lpc_add_io_resources(dev);
+
+	/* Allocate ACPI NVS in CBMEM */
+	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
 }
 
 static struct device_operations device_ops = {
 	.read_resources = &soc_lpc_read_resources,
 	.set_resources = &pci_dev_set_resources,
 	.enable_resources = &pci_dev_enable_resources,
+	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
 	.write_acpi_tables = southbridge_write_acpi_tables,
 };