[coreboot-gerrit] New patch to review for coreboot: intel/apollolake_rvp: Write GPIO lb table for CHROMEOS builds

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13402

-gerrit

commit 2dcc298e377495d799f64fb13395c3b78b315923
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date:   Wed Jan 13 14:30:03 2016 -0800

    intel/apollolake_rvp: Write GPIO lb table for CHROMEOS builds
    
    Note that the table only defines the entries, but does not link them
    to real GPIOs. This is enough for the deptcharge payload to not crash
    during boot.
    
    Change-Id: Ib9d73d873b0a864bcb8ab7061514c0bab7af27bf
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/mainboard/intel/apollolake_rvp/Makefile.inc    |  1 +
 .../intel/apollolake_rvp/chromeos_ramstage.c       | 32 ++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc
index 52de59b..e30e19a 100755
--- a/src/mainboard/intel/apollolake_rvp/Makefile.inc
+++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc
@@ -1,5 +1,6 @@
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c
 
 ramstage-y += mainboard.c
diff --git a/src/mainboard/intel/apollolake_rvp/chromeos_ramstage.c b/src/mainboard/intel/apollolake_rvp/chromeos_ramstage.c
new file mode 100644
index 0000000..81866a8
--- /dev/null
+++ b/src/mainboard/intel/apollolake_rvp/chromeos_ramstage.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#define GPIO_COUNT 7
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio *gpio;
+
+	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+	gpios->count = GPIO_COUNT;
+
+	gpio = gpios->gpios;
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", 0);
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", 1);
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1);
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", 0);
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", 0);
+}