[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: Thermal Design Power PL1 and PL2 Config Changes

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f9495eae2c9a0894fb7a8917779880830b27a224
Author: pchandri <preetham.chandrian at intel.com>
Date:   Mon Jan 11 15:22:45 2016 -0800

    intel/skylake: Thermal Design Power PL1 and PL2 Config Changes
    
    Override the default PL2 values with one recommended by
    Intel. Disable PL1 configuration via MMIO register.
    
    BUG=chrome-os-partner:49292
    BRANCH=glados
    TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W
    MMIO 0x59A0[15] to find PL1 enable/disable = Disable
    MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W
    Here PL2 is set to 25W and PL1 is disabled.
    
    Change-Id: I10742f91cc7179de1482d42392338976e8082afe
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 1b7771ccb34bdff92ffa9870733bd641e4644cdf
    Original-Change-Id: Iefa93912008c71b41f2b20465e8acfd42bb6c731
    Original-Signed-off-by: pchandri <preetham.chandrian at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/321392
    Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
    Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
    Reviewed-on: https://review.coreboot.org/13070
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/13070 for details.

-gerrit