[coreboot-gerrit] Patch merged into coreboot/master: google/veyron_*: Add dual-rank 2GB Hynix module to SDRAM configs

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 2cd9c05dc10462c105d889cecc148b5d87ac53fb
Author: David Hendricks <dhendrix at chromium.org>
Date:   Tue Jan 12 22:01:13 2016 -0800

    google/veyron_*: Add dual-rank 2GB Hynix module to SDRAM configs
    
    This is a follow-up to CL:320623 to make veyron DRAM configs
    uniform (except for Rialto).
    
    As discussed in chrome-os-partner:43626, the mr[3] value and ODT
    are set diffently for Mickey, thus the .inc files for other boards
    have mr[3] = 1 and ODT disabled.
    
    BUG=none
    BRANCH=veyron
    TEST=compile tested for veyron
    
    Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb
    Original-Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab
    Original-Reviewed-on: https://chromium-review.googlesource.com/321870
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: https://review.coreboot.org/13109
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix at chromium.org>


See https://review.coreboot.org/13109 for details.

-gerrit