[coreboot-gerrit] Patch merged into coreboot/master: google/chell: Set FSP params for min assertion widths and serirq

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit a0ee532af76d5ecca3d87b080513d84695dc5321
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Jan 7 16:53:43 2016 -0800

    google/chell: Set FSP params for min assertion widths and serirq
    
    - Enable serial irq configuration in FSP.
    - Set minimum assertion width values for FSP to configure.
    - Set I2C4 voltage to 1.8V.
    - Enable SaGv feature to dynamically train memory frequency.
    
    BUG=chrome-os-partner:47688
    BRANCH=none
    TEST=build and boot on chell EVT
    
    Change-Id: If6955c9ee4f08d1ebc6e98e0ba0786073919856f
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7403149299ec2c6c66c2066a5dd8294608e71409
    Original-Change-Id: Ia182396ad4eb7a283e183fce7c50c98f6d2de57c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/321212
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/13009
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/13009 for details.

-gerrit