[coreboot-gerrit] Patch set updated for coreboot: google/chell: Enable eMMC HS400 mode

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13003

-gerrit

commit 18e92165ef852154dbbc058ec1a6873c5b9027c1
Author: Ryan Lin <ryan.lin at intel.com>
Date:   Fri Dec 25 10:54:44 2015 +0800

    google/chell: Enable eMMC HS400 mode
    
    Hynix eMMC can now run under HS400 mode.
    
    BUG=chrome-os-partner:47647
    TEST=run consective boot 100 times on Chell EVT Hynix SKU, and
    MMC errors didn't happen.
    BRANCH=none
    
    Change-Id: Icb6fc03d0510d2c5aeb5b08ed7189e954ab39a72
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9966c430a508a13cf1a617f485a48866bec161ca
    Original-Change-Id: I6bec88f5c2813131a693ddba5523a9d43b2ebd45
    Original-Signed-off-by: Ryan Lin <ryan.lin at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/319627
    Original-Commit-Ready: Duncan Laurie <dlaurie at chromium.org>
    Original-Tested-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/chell/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 81df06f..ceb1160 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -35,7 +35,7 @@ chip soc/intel/skylake
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "1"
-	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsEmmcHs400Enabled" = "1"
 	register "ScsSdCardEnabled" = "0"
 	register "IshEnable" = "0"
 	register "PttSwitch" = "0"