[coreboot-gerrit] Patch set updated for coreboot: google/chell: Enable FspSkipMpInit token

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13000

-gerrit

commit d77fe0347ea288c5fdf5ea7249e7c678ace3ee4f
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Fri Dec 18 16:29:59 2015 +0530

    google/chell: Enable FspSkipMpInit token
    
    MP init is already handled in coreboot, but it is also part of FSP
    FSP has a implemented a provision to allow FSP to skip MP init and
    let coreboot handle it.
    
    BRANCH=none
    BUG=chrome-os-partner:44805
    TEST=none
    
    CQ-DEPEND=CL:319353
    
    Change-Id: I22c1add182b299e2ad9d413bc13c5a5acc6a3179
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: ccf89c9d1fe18b74c385e7d12a6aef5b63d7b243
    Original-Change-Id: I53b754fd10a140588ad67d9292d9bc04a6d43677
    Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/319194
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/chell/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index f43d6c8..81df06f 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -43,6 +43,7 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
+	register "FspSkipMpInit" = "1"
 
 	# VR Settings Configuration for 5 Domains
 	#+----------------+-------+-------+-------------+-------------+-------+