[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: Add devicetree setting for DDR frequency limit UPD

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit ddd9f1a5a65db7a461ffb6576ca45acf56c2b000
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Dec 10 01:01:59 2015 -0800

    intel/skylake: Add devicetree setting for DDR frequency limit UPD
    
    There is a UPD setting exposed by FSP that allows the DDR
    frequency to be limited.  Expose this for devicetree.
    
    BUG=chrome-os-partner:47346
    BRANCH=none
    TEST=tested by limiting DDR frequency to 1600 on chell EVT
    
    Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220
    Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/317243
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/12981
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/12981 for details.

-gerrit