[coreboot-gerrit] New patch to review for coreboot: google/lars: Enable SaGv feature

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13002

-gerrit

commit 5a39c3aaf4c99cdaca679057e2b340b78dee7d22
Author: david <david_wu at quantatw.com>
Date:   Mon Dec 28 20:28:58 2015 +0800

    google/lars: Enable SaGv feature
    
    This change enables SaGv feature for skylake
    platform.As a result of this patch the skylake
    platform will train memory at both low & high
    frequency points.This will be used to
    dynamically scale the work point
    (voltage/frequencies).
    
    The value "3" here means enable. Following
    is the table for same.
    
    0=Disabled(SaGv disabled)
    1=FixedLow(Fixed to low frequency)
    2=FixedHigh(Fixed to High frequency)
    3=Enabled(SaGv Enabled.Dynamically changes)
    
    BRANCH=None
    BUG=chrome-os-partner:48534
    TEST=Build and boot lars
    
    Change-Id: I82b1a428d2d3dce47f46de576f677cf2249b6b5d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8e252123cc73543d0f1b320af9d8873f99a45ab1
    Original-Change-Id: I1a545ff2f38df23964378c0d833e29006b2c5557
    Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/320022
    Original-Commit-Ready: David Wu <david_wu at quantatw.com>
    Original-Tested-by: David Wu <david_wu at quantatw.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala at intel.com>
---
 src/mainboard/google/lars/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index ed47820..689babb 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -30,6 +30,7 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
+	register "SaGv" = "3"
 	register "FspSkipMpInit" = "1"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch