[coreboot-gerrit] New patch to review for coreboot: google/glados: Add pull-ups on LPC address lines and setup PCH_WP early

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12982

-gerrit

commit 787ef05d603b21b5e9d14b57fcd687b5f7827590
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Dec 10 01:03:21 2015 -0800

    google/glados: Add pull-ups on LPC address lines and setup PCH_WP early
    
    Copy changes from chell to add 20K pull-up to LPC address lines
    and setup the PCH_WP signal early so it is set correctly in VBNV.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I3337cb9e5ee445471c7a0b61ee22869f66189b63
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c99dae3729636790c2ad457ec3271d2bd99fb1c4
    Original-Change-Id: I7627ec263e710ce186cea15c805203395acf3e99
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/317244
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/gpio.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
index cd7a936..5ea6691 100644
--- a/src/mainboard/google/glados/gpio.h
+++ b/src/mainboard/google/glados/gpio.h
@@ -57,10 +57,10 @@
 /* Pad configuration in ramstage. */
 static const struct pad_config gpio_table[] = {
 /* RCIN# */		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-/* LAD0 */		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
-/* LAD1 */		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
-/* LAD2 */		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
-/* LAD3 */		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+/* LAD0 */		PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
+/* LAD1 */		PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
+/* LAD2 */		PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
+/* LAD3 */		PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
 /* LFRAME# */		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 /* SERIRQ */		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
 /* PIRQA# */		/* GPP_A7 */