[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Add devicetree setting for DDR frequency limit UPD

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12981

-gerrit

commit 2c2a7d2f105455263807acccd42a8e4418d114d0
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Dec 10 01:01:59 2015 -0800

    intel/skylake: Add devicetree setting for DDR frequency limit UPD
    
    There is a UPD setting exposed by FSP that allows the DDR
    frequency to be limited.  Expose this for devicetree.
    
    BUG=chrome-os-partner:47346
    BRANCH=none
    TEST=tested by limiting DDR frequency to 1600 on chell EVT
    
    Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220
    Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/317243
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.h              | 6 ++++++
 src/soc/intel/skylake/romstage/romstage.c | 1 +
 2 files changed, 7 insertions(+)

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 1c45470..7e401eb 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -113,6 +113,12 @@ struct soc_intel_skylake_config {
 	u32 TsegSize;
 	u16 MmioSize;
 
+	/*
+	 * DDR Frequency Limit
+	 * 0(Auto), 1067, 1333, 1600, 1867, 2133, 2400
+	 */
+	u16 DdrFreqLimit;
+
 	/* Probeless Trace function */
 	u8 ProbelessTrace;
 
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 5481004..31f7fc2 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -92,6 +92,7 @@ void soc_memory_init_params(struct romstage_params *params,
 	upd->EnableTraceHub = config->EnableTraceHub;
 	upd->SaGv = config->SaGv;
 	upd->RMT = config->Rmt;
+	upd->DdrFreqLimit = config->DdrFreqLimit;
 }
 
 void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,