[coreboot-gerrit] New patch to review for coreboot: intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12957

-gerrit

commit 42b32394956426f1ae7cfa3afc8dcb8438eafbdd
Author: pchandri <preetham.chandrian at intel.com>
Date:   Mon Nov 30 13:05:53 2015 -0800

    intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3
    
    At S0, S0ix and S3 LPC LAD signals are
    are floated at 400~500mV.
    
    BRANCH=chrome-os-partner:48331
    BUG=None
    TEST=Build and Boot kunimitsu
    
    Change-Id: I2e2654ac89f8e0c8d6ab1af31d0bd5a0d4c43db8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6f4b902e220dcde73df56970208c45fe3148b70e
    Original-Change-Id: I597d4816d09d0cfd9b0ec183a9273551aed8688a
    Original-Signed-off-by: pchandri <preetham.chandrian at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/316529
    Original-Commit-Ready: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Tested-by: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Tested-by: Kyoung Il Kim <kyoung.il.kim at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
    Original-Reviewed-by: Kyoung Il Kim <kyoung.il.kim at intel.com>
---
 src/mainboard/intel/kunimitsu/gpio.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index f027326..1470ba6 100755
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -62,10 +62,10 @@
 /* Pad configuration in ramstage. */
 static const struct pad_config gpio_table[] = {
 /* EC_PCH_RCIN */	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-/* LPC_LAD_0 */		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
-/* LPC_LAD_1 */		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
-/* LPC_LAD_2 */		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
-/* LPC_LAD_3 */		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+/* LPC_LAD_0 */		PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
+/* LPC_LAD_1 */		PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
+/* LPC_LAD_2 */		PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
+/* LPC_LAD_3 */		PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
 /* LPC_FRAME */		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 /* LPC_SERIRQ */	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
 /* SD_CD_WAKE */	PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),