[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Add GPIO ACPI Apis.
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Jan 14 11:06:19 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12956
-gerrit
commit 8375241fcdc19e926bce41fc905bccb4eeac818a
Author: Subrata Banik <subrata.banik at intel.com>
Date: Mon Dec 7 19:49:01 2015 +0530
intel/skylake: Add GPIO ACPI Apis.
GPIO ASL APIs to get GPIO Value.
Need such APIs to read GPIO config settings.
Example: Kunimitsu need to read AUDIO_DB GPIO
to identify codec select.
BUG=chrome-os-partner:44481
BRANCH=none
TEST=build and boot on Kunimitsu.
Change-Id: If56bb7b3eae08e1949d372850a6426dfde5aadd0
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 4983ba835a8da2baf578b035ae482755983c1ecb
Original-Change-Id: Ia40d86c8d4b14857fa8822677b3f7d393a35b677
Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316352
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/skylake/acpi/gpio.asl | 46 +++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl
index 42f2ee7..d305e91 100644
--- a/src/soc/intel/skylake/acpi/gpio.asl
+++ b/src/soc/intel/skylake/acpi/gpio.asl
@@ -13,6 +13,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
+#include <soc/gpio_defs.h>
Device (GPIO)
{
@@ -67,3 +68,48 @@ Device (GPIO)
Return (0xF)
}
}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+ /* GPIO Community 0 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23)))
+ {
+ Store (PID_GPIOCOM0, Local0)
+ Subtract (Arg0, GPP_A0, Local1)
+ }
+ /* GPIO Community 1 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23)))
+ {
+ Store (PID_GPIOCOM1, Local0)
+ Subtract (Arg0, GPP_C0, Local1)
+ }
+ /* GPIO Community 03*/
+ If (LAnd (LGreaterEqual (Arg0, GPP_F0), LLessEqual (Arg0, GPP_G7)))
+ {
+ Store (PID_GPIOCOM3, Local0)
+ Subtract (Arg0, GPP_F0, Local1)
+ }
+ Store (PCRB (Local0), Local2)
+ Add (Local2, PAD_CFG_DW_OFFSET, Local2)
+ Return (Add (Local2, Multiply (Local1, 8)))
+}
+
+/*
+ * Get GPIO Value
+ * Arg0 - GPIO Number
+ */
+Method (GRXS, 1, NotSerialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)
+
+ Return (Local0)
+}
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