[coreboot-gerrit] New patch to review for coreboot: fsp_baytrail: Add additional PCI space above 4GB

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12868

-gerrit

commit 777db72d761508d3f84d89761e665177a9f13e28
Author: Martin Roth <martinroth at google.com>
Date:   Tue Dec 22 12:40:53 2015 -0700

    fsp_baytrail: Add additional PCI space above 4GB
    
    This just tells the OS that it can use the 16GB of address space
    at the 48GB mark for PCI.  This is the upper 16GB of Bay Trail's 36 bit
    physical address space.
    
    This could be hardcoded into the UMEM definition, but doing it this way
    makes it more plain what it's doing, and allows for modification
    to put it just above the top of upper memory, similar to what is done
    with the standard PCI region above the top of low memory.
    
    Change-Id: Idb17ea919eb71e31c5f1a2f08599a412825b9c25
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Original-Commit-Id:
    Original-Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad
    Original-Signed-off-by: Martin Roth <martinroth at google.com>
    Original-Reviewed-on: https://review.coreboot.org/12791
    Original-Tested-by: build bot (Jenkins)
    Original-Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Original-Reviewed-by: York Yang <york.yang at intel.com>
---
 src/soc/intel/fsp_baytrail/acpi/southcluster.asl | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
index 2fbdb16..a38b742 100644
--- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
@@ -163,6 +163,12 @@ Name (MCRS, ResourceTemplate()
 			Cacheable, ReadWrite,
 			0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
 			0x00005000,,, TPMR)
+
+	// High PCI Memory Region
+	QwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+			Cacheable, ReadWrite,
+			0x00000000, 0x00000000, 0x00000000, 0x00000000,
+			0x00000000,,, UMEM)
 })
 
 Method (_CRS, 0, Serialized)
@@ -177,6 +183,15 @@ Method (_CRS, 0, Serialized)
 	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
 	Add (Subtract (PMAX, PMIN), 1, PLEN)
 
+	// Update High PCI resource area
+	CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
+	CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
+	CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
+
+	Store(0x40000000 * 48, UMIN)	// Set base address to 48GB
+	Store(0x40000000 * 16, ULEN)	// Allocate 16GB for PCI space
+	Add(UMIN, Subtract(ULEN, 1), UMAX)
+
 	Return (MCRS)
 }