[coreboot-gerrit] Patch set updated for coreboot: Correct some common spelling mistakes
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Wed Jan 6 17:14:47 CET 2016
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12850
-gerrit
commit eb65dfbe093b738d472f8073a2cf7e0318b6a6f7
Author: Martin Roth <martinroth at google.com>
Date: Tue Jan 5 20:58:58 2016 -0700
Correct some common spelling mistakes
- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller
Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth at google.com>
---
src/arch/arm/armv7/bootblock.S | 2 +-
src/arch/x86/exception.c | 2 +-
src/device/azalia_device.c | 2 +-
src/include/console/post_codes.h | 2 +-
src/lib/imd.c | 2 +-
src/mainboard/via/vt8454c/devicetree.cb | 2 +-
src/northbridge/amd/amdk8/thermal_mixin.asl | 2 +-
src/northbridge/amd/amdmct/mct/mctecc_d.c | 2 +-
src/northbridge/intel/i945/raminit.c | 58 +++++++++++++-------------
src/northbridge/intel/x4x/raminit.c | 2 +-
src/northbridge/via/vx900/sata.c | 2 +-
src/soc/broadcom/cygnus/ddr_init.c | 2 +-
src/soc/intel/braswell/smihandler.c | 2 +-
src/soc/intel/skylake/smihandler.c | 2 +-
src/soc/nvidia/tegra124/clock.c | 2 +-
src/soc/nvidia/tegra132/clock.c | 2 +-
src/southbridge/amd/pi/hudson/smihandler.c | 2 +-
src/southbridge/intel/bd82x6x/smihandler.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/smihandler.c | 2 +-
src/southbridge/intel/fsp_i89xx/smihandler.c | 2 +-
src/southbridge/intel/i82801dx/smihandler.c | 2 +-
src/southbridge/intel/i82801gx/lpc.c | 4 +-
src/southbridge/intel/i82801ix/early_init.c | 2 +-
src/southbridge/intel/i82801ix/i82801ix.h | 2 +-
src/southbridge/intel/i82801ix/smihandler.c | 2 +-
src/southbridge/intel/ibexpeak/smihandler.c | 2 +-
src/southbridge/intel/lynxpoint/smihandler.c | 2 +-
src/southbridge/intel/sch/audio.c | 2 +-
src/superio/winbond/w83627hf/acpi/superio.asl | 2 +-
29 files changed, 58 insertions(+), 58 deletions(-)
diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
index 16d7b92..ad7085d 100644
--- a/src/arch/arm/armv7/bootblock.S
+++ b/src/arch/arm/armv7/bootblock.S
@@ -91,7 +91,7 @@ call_bootblock:
ldr r0,=0x00000000
/*
* The current design of cpu_info places the struct at the top of the
- * stack. Free enough space to accomodate for that, but make sure it's
+ * stack. Free enough space to accommodate for that, but make sure it's
* 8-byte aligned for ABI compliance.
*/
sub sp, sp, #16
diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
index 65181e2..d675eba 100644
--- a/src/arch/x86/exception.c
+++ b/src/arch/x86/exception.c
@@ -385,7 +385,7 @@ void x86_exception(struct eregs *info)
signo = exception_to_signal[info->vector];
}
- /* reply to the host that an exception has occured */
+ /* reply to the host that an exception has occurred */
out_buffer[0] = 'S';
out_buffer[1] = hexchars[(signo>>4) & 0xf];
out_buffer[2] = hexchars[signo & 0xf];
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index dab1038..5c2fcfc 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -78,7 +78,7 @@ static int codec_detect(u8 *base)
mdelay(1);
reg32 = read32(base + 0x0E);
} while ((reg32 != 0) && --count);
- /* Timeout occured */
+ /* Timeout occurred */
if (!count)
goto no_codec;
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index e6d1243..d689ff3 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -311,7 +311,7 @@
* If the payload was built out-of-tree, check that it was compiled as
* a coreboot payload
* \n
- * Check the console output to see exactly where the failure occured.
+ * Check the console output to see exactly where the failure occurred.
*/
#define POST_DIE 0xff
diff --git a/src/lib/imd.c b/src/lib/imd.c
index 2ad9cd8..2fc6fac 100644
--- a/src/lib/imd.c
+++ b/src/lib/imd.c
@@ -159,7 +159,7 @@ static int imdr_create_empty(struct imdr *imdr, size_t root_size,
return -1;
/*
- * root_size needs to be large enough to accomodate root pointer and
+ * root_size needs to be large enough to accommodate root pointer and
* root book keeping structure. The caller needs to ensure there's
* enough room for tracking individual allocations.
*/
diff --git a/src/mainboard/via/vt8454c/devicetree.cb b/src/mainboard/via/vt8454c/devicetree.cb
index efb5b6c..31cb11e 100644
--- a/src/mainboard/via/vt8454c/devicetree.cb
+++ b/src/mainboard/via/vt8454c/devicetree.cb
@@ -45,7 +45,7 @@ chip northbridge/via/cx700
end
end # superio
end # pci 11.0
- # 1-4 non existant
+ # 1-4 non existent
#device pci 11.5 on end # AC97 Audio
#device pci 11.6 off end # AC97 Modem
#device pci 12.0 on end # Ethernet
diff --git a/src/northbridge/amd/amdk8/thermal_mixin.asl b/src/northbridge/amd/amdk8/thermal_mixin.asl
index 97bc760..f096e5d 100644
--- a/src/northbridge/amd/amdk8/thermal_mixin.asl
+++ b/src/northbridge/amd/amdk8/thermal_mixin.asl
@@ -45,7 +45,7 @@
OperationRegion(K8TR, PCI_Config, 0xE4, 0x4)
Field(K8TR, DWordAcc, NoLock, Preserve) {
, 1,
- THTP, 1, /* Temperature sensor trip occured */
+ THTP, 1, /* Temperature sensor trip occurred */
CORE, 1, /* Select Core */
TTS0, 1, /* Temperature sensor trip on CPU1 (or single core CPU0) */
TTS1, 1, /* Temperature sensor trip on CPU0 */
diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c
index b54ba4b..b2ac849 100644
--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c
@@ -275,7 +275,7 @@ static u32 GetScrubAddr_D(u32 Node)
/* Scrub Addr High again, detect 32-bit wrap */
val = Get_NB32(dev, reg);
if(val != hi) {
- hi = val; /* Scrub Addr Low again, if wrap occured */
+ hi = val; /* Scrub Addr Low again, if wrap occurred */
lo = Get_NB32(dev, regx);
}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b1bd2ec..59a31de 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2167,8 +2167,8 @@ static void sdram_program_clock_crossing(void)
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
0x08040120, 0x00000000, /* DDR400 FSB533 */
0x00100401, 0x00000000, /* DDR533 FSB533 */
@@ -2178,51 +2178,51 @@ static void sdram_program_clock_crossing(void)
0x10040280, 0x00000040, /* DDR533 FSB667 */
0x00100401, 0x00000000, /* DDR667 FSB667 */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
};
static const u32 command_clock_crossing[] = {
0x04020208, 0x00000000, /* DDR400 FSB400 */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
0x00060108, 0x00000000, /* DDR400 FSB533 */
0x04020108, 0x00000000, /* DDR533 FSB533 */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
0x00040318, 0x00000000, /* DDR400 FSB667 */
0x04020118, 0x00000000, /* DDR533 FSB667 */
0x02010804, 0x00000000, /* DDR667 FSB667 */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
};
#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
/* i945 G/P */
static const u32 data_clock_crossing[] = {
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
0x10080201, 0x00000000, /* DDR400 FSB533 */
0x00100401, 0x00000000, /* DDR533 FSB533 */
0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
0x04020108, 0x00000000, /* DDR400 FSB800 */
0x00020108, 0x00000000, /* DDR533 FSB800 */
@@ -2234,17 +2234,17 @@ static void sdram_program_clock_crossing(void)
};
static const u32 command_clock_crossing[] = {
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
0x00010800, 0x00000402, /* DDR400 FSB533 */
0x01000400, 0x00000200, /* DDR533 FSB533 */
0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
+ 0xffffffff, 0xffffffff, /* nonexistent */
0x02010804, 0x00000000, /* DDR400 FSB800 */
0x00010402, 0x00000000, /* DDR533 FSB800 */
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 613011f..f5a4e5f 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -38,7 +38,7 @@ static void sdram_read_spds(struct sysinfo *s)
int status = 0;
FOR_EACH_DIMM(i) {
if (s->spd_map[i] == 0) {
- /* Non-existant SPD address */
+ /* Non-existent SPD address */
s->dimms[i].card_type = 0;
continue;
}
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
index 27f0791..98e4bd2 100644
--- a/src/northbridge/via/vx900/sata.c
+++ b/src/northbridge/via/vx900/sata.c
@@ -36,7 +36,7 @@ static void vx900_print_sata_errors(u32 flags)
printk(BIOS_DEBUG, "\tCOMWAKE %s\n",
(flags & (1 << 16)) ? "detected" : "not detected");
printk(BIOS_DEBUG, "\tExchange as determined by COMINIT %s\n",
- (flags & (1 << 26)) ? "occured" : "not occured");
+ (flags & (1 << 26)) ? "occurred" : "not occurred");
printk(BIOS_DEBUG, "\tPort selector presence %s\n",
(flags & (1 << 27)) ? "detected" : "not detected");
/* Errors */
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c
index f885cec..b08e3c0 100755
--- a/src/soc/broadcom/cygnus/ddr_init.c
+++ b/src/soc/broadcom/cygnus/ddr_init.c
@@ -1178,7 +1178,7 @@ static int clear_ddr(uint32_t offset, uint32_t size)
}
printk(BIOS_INFO, "clear_ddr: Failed: 0x%lx\n", get_timer(start));
if(reg32_read((volatile uint32_t *)DDR_BistErrorOccurred))
- printk(BIOS_ERR, "clear_ddr: Error occured\n");
+ printk(BIOS_ERR, "clear_ddr: Error occurred\n");
return(1);
}
#endif /* CONFIG_IPROC_DDR_ECC */
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index b637420..dabc0d2 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -461,7 +461,7 @@ void southbridge_smi_handler(void)
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG,
- "SMI_STS[%d] occured, but no "
+ "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
}
}
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 19bb995..c5e6c82 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -509,7 +509,7 @@ void southbridge_smi_handler(void)
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG,
- "SMI_STS[%d] occured, but no handler available.\n",
+ "SMI_STS[%d] occurred, but no handler available.\n",
i);
}
}
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index de7b218..4c087b8 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -389,7 +389,7 @@ clock_display(u32 frequency)
/* Initialize the UART and put it on CLK_M so we can use it during clock_init().
* Will later move it to PLLP in clock_config(). The divisor must be very small
- * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
+ * to accommodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
* CLK_SOURCE divider to get more precision. (This might still not be enough for
* some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has
* been determined through trial and error (must lead to div 13 at 24MHz). */
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index 73b05e0..0db120d 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -389,7 +389,7 @@ u32 clock_configure_plld(u32 frequency)
/* Initialize the UART and put it on CLK_M so we can use it during clock_init().
* Will later move it to PLLP in clock_config(). The divisor must be very small
- * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
+ * to accommodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
* CLK_SOURCE divider to get more precision. (This might still not be enough for
* some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has
* been determined through trial and error (must lead to div 13 at 24MHz). */
diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c
index 6f2504b..af8c215 100644
--- a/src/southbridge/amd/pi/hudson/smihandler.c
+++ b/src/southbridge/amd/pi/hudson/smihandler.c
@@ -64,7 +64,7 @@ static void process_gpe_smi(void)
/* Only Bits [23:0] indicate GEVENT SMIs. */
if (status & gevent_mask) {
- /* A GEVENT SMI occured */
+ /* A GEVENT SMI occurred */
mainboard_smi_gpi(status & gevent_mask);
}
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 098e8d4..f6fbac3 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -855,7 +855,7 @@ void southbridge_smi_handler(void)
if (southbridge_smi[i]) {
southbridge_smi[i]();
} else {
- printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
+ printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
dump = 1;
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index cbeff9d..c320a0b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -742,7 +742,7 @@ void southbridge_smi_handler(void)
if (southbridge_smi[i]) {
southbridge_smi[i]();
} else {
- printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
+ printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
dump = 1;
}
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index b2cd07b..2c7ece2 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -743,7 +743,7 @@ void southbridge_smi_handler(void)
if (southbridge_smi[i]) {
southbridge_smi[i]();
} else {
- printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
+ printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
dump = 1;
}
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 34a5231..dcd3df1 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -629,7 +629,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
if (southbridge_smi[i])
southbridge_smi[i](node, state_save);
else {
- printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
+ printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
dump = 1;
}
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 4e9711c..03df1a3 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -42,7 +42,7 @@
typedef struct southbridge_intel_i82801gx_config config_t;
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
@@ -200,7 +200,7 @@ static void i82801gx_power_options(device_t dev)
}
reg8 |= (3 << 4); /* avoid #S4 assertions */
- reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */
+ reg8 &= ~(1 << 3); /* minimum assertion is 1 to 2 RTCCLK */
pci_write_config8(dev, GEN_PMCON_3, reg8);
printk(BIOS_INFO, "Set power %s after power failure.\n", state);
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index 1d6c649..3d94b56 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -42,7 +42,7 @@ void i82801ix_early_init(void)
/* Enable upper 128bytes of CMOS. */
RCBA32(0x3400) = (1 << 2);
- /* Initialize power manangement initialization
+ /* Initialize power management initialization
register early as it affects reboot behavior. */
/* Bit 20 activates global reset of host and ME on cf9 writes of 0x6
and 0xe (required if ME is disabled but present), bit 31 locks it.
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index d5bcbc2..afe4aa7 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -193,7 +193,7 @@
#define RCBA_FD 0x3418 /* Function Disable, see below. */
#define RCBA_CG 0x341c
#define RCBA_FDSW 0x3420
-#define RCBA_MAP 0x35f0 /* UHCI cotroller #6 remapping */
+#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */
#define BUC_LAND (1 << 5) /* LAN */
#define FD_SAD2 (1 << 25) /* SATA #2 */
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 7beb999..9e04328 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -511,7 +511,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
if (southbridge_smi[i])
southbridge_smi[i](node, state_save);
else {
- printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
+ printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
dump = 1;
}
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 04ef75d..fb96930 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -842,7 +842,7 @@ void southbridge_smi_handler(void)
if (southbridge_smi[i]) {
southbridge_smi[i]();
} else {
- printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
+ printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
dump = 1;
}
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 5e85ca5..c8dc454 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -530,7 +530,7 @@ void southbridge_smi_handler(void)
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG,
- "SMI_STS[%d] occured, but no "
+ "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
}
}
diff --git a/src/southbridge/intel/sch/audio.c b/src/southbridge/intel/sch/audio.c
index 11950ad..765d8de 100644
--- a/src/southbridge/intel/sch/audio.c
+++ b/src/southbridge/intel/sch/audio.c
@@ -81,7 +81,7 @@ static int codec_detect(u8 *base)
mdelay(1);
reg32 = read32(base + 0x0E);
} while ((reg32 != 0) && --count);
- /* Timeout occured */
+ /* Timeout occurred */
if (!count)
goto no_codec;
diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl
index f6509d4..ef4504c 100644
--- a/src/superio/winbond/w83627hf/acpi/superio.asl
+++ b/src/superio/winbond/w83627hf/acpi/superio.asl
@@ -17,7 +17,7 @@
* include this file into a mainboard's DSDT _SB device tree and it will expose the
* W83627HF SuperIO and its functionality.
*
- * Devices are marked as nonexistant if they got 0x00000000 as I/O base address
+ * Devices are marked as nonexistent if they got 0x00000000 as I/O base address
* (compatibility with legacy bios, which disables logical devices that way)
*
* It allows the change of IO ports, IRQs and DMA settings on most logical
More information about the coreboot-gerrit
mailing list