[coreboot-gerrit] Patch merged into coreboot/master: riscv: enable counters via m[us]counteren

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f171e6645df0ed9bc214b408eca7e8fdc7c04075
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Mon Dec 19 09:06:00 2016 -0800

    riscv: enable counters via m[us]counteren
    
    The user and supervisor counters could not be safely enabled
    before as the register numbers were not finalized. Now that
    everyone agrees, we can enable them. Until we are sure the
    toolchains are caught up, we use the hardcode name with
    the register names in comments. As soon as toolchains
    settle down we'll do one more pass and convert to
    the symbolic names.
    
    Tested on lowrisc bitstream and SPIKE simulator.
    
    Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
    Reviewed-on: https://review.coreboot.org/17920
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alex Bradbury <asb at lowrisc.org>
    Reviewed-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
    Reviewed-by: Andrew Waterman <aswaterman at gmail.com>


See https://review.coreboot.org/17920 for details.

-gerrit