[coreboot-gerrit] Patch set updated for coreboot: mainboard/glkrvp: Add GLKRVP board specific gpios
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Tue Dec 13 22:17:23 CET 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17818
-gerrit
commit 04f9053632dd5d283c8b579678906c9a832237a8
Author: Hannah Williams <hannah.williams at intel.com>
Date: Mon Oct 10 15:11:39 2016 -0700
mainboard/glkrvp: Add GLKRVP board specific gpios
Change-Id: I38966ce1b42eca22757dbf0b1268a385d47ca6c2
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
.../intel/glkrvp/variants/baseboard/gpio.c | 456 ++++++++++++++++++++-
.../variants/baseboard/include/baseboard/gpio.h | 14 +-
2 files changed, 456 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
index 69a44b6..c5ef57f 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
@@ -23,6 +23,452 @@
* the table so those were moved for more logical grouping.
*/
static const struct pad_config gpio_table[] = {
+/* NORTHWEST COMMUNITY GPIOS */
+ GLK_GPIO_PAD_CONF("TCK", GPIO_0, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("TRST_B", GPIO_1, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("TMS", GPIO_2, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("TDI", GPIO_3, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("TDO",GPIO_4, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("JTAGX", GPIO_5, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("CX_PREQ_B", GPIO_6, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("CX_PRDY_B", GPIO_7, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("GPIO_8", GPIO_8, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_CLK_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_9", GPIO_9, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA0_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_10", GPIO_10, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA1_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_11", GPIO_11, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA2_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_12", GPIO_12, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA3_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_13", GPIO_13, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA4_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_14", GPIO_14, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA5_VNN */
+ GLK_GPIO_PAD_CONF("GPIO_15", GPIO_15, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA6_VNN */
+ GLK_GPIO_PAD_CONF("GPIO_16", GPIO_16, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA7_VNN */
+ GLK_GPIO_PAD_CONF("GPIO_17", GPIO_17, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* Ec-to-SOC CS Wake */
+ GLK_GPIO_PAD_CONF("GPIO_18", GPIO_18, M0, GPI, ACPI_D, NA, LEVEL,
+ WAKE_ENABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Touch Pad Interrupt */
+ GLK_GPIO_PAD_CONF("GPIO_19", GPIO_19, M0, GPI, ACPI_D, NA, EDGE,
+ WAKE_DISABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_IOAPIC, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* PMIC Interrupt- Reserved for RVP2 */
+ GLK_GPIO_PAD_CONF("GPIO_20", GPIO_20, M0, GPI, ACPI_D, NA, LEVEL,
+ WAKE_ENABLED, P_NONE,
+ NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),/* Audio Codec Interrupt*/
+ GLK_GPIO_PAD_CONF("GPIO_21", GPIO_21, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_RXD */
+ GLK_GPIO_PAD_CONF("GPIO_22", GPIO_22, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_TXD */
+ GLK_GPIO_PAD_CONF("GPIO_23", GPIO_23, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_GNSS_PABLANKIt */
+ GLK_GPIO_PAD_CONF("GPIO_24", GPIO_24, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("GPIO_25", GPIO_25, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*WWAN /RF_KILL_GPS*/
+ GLK_GPIO_PAD_CONF("GPIO_26", GPIO_26, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* NFC Interrupt */
+ GLK_GPIO_PAD_CONF("GPIO_27", GPIO_27, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_WiFi/WiFi_Disable */
+ GLK_GPIO_PAD_CONF("GPIO_28", GPIO_28, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_BT/BT_Disable */
+ GLK_GPIO_PAD_CONF("GPIO_29", GPIO_29, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* Codec Power Down: Ouput/ISH_GPIO_3*/
+ GLK_GPIO_PAD_CONF("GPIO_30", GPIO_30, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_4 */
+ GLK_GPIO_PAD_CONF("GPIO_31", GPIO_31, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_5 */
+ GLK_GPIO_PAD_CONF("GPIO_32", GPIO_32, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_6 */
+ GLK_GPIO_PAD_CONF("GPIO_33", GPIO_33, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_7 */
+ GLK_GPIO_PAD_CONF("GPIO_34", GPIO_34, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_8/SUSCLK2 (1.8V) */
+ GLK_GPIO_PAD_CONF("GPIO_35", GPIO_35, M6, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_CLK */
+ GLK_GPIO_PAD_CONF("GPIO_36", GPIO_36, M6, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_DI */
+ GLK_GPIO_PAD_CONF("GPIO_37", GPIO_37, M0, GPI, ACPI_D, NA,
+ EDGE, WAKE_ENABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_SCI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Runtime SCI */
+ GLK_GPIO_PAD_CONF("GPIO_38", GPIO_38, M0, GPI, ACPI_D, NA,
+ EDGE, WAKE_ENABLED, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Wake SCI */
+ GLK_GPIO_PAD_CONF("GPIO_39", GPIO_39, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* Finger Print Sensor Interrupt (DRDY) */
+ GLK_GPIO_PAD_CONF("GPIO_40", GPIO_40, M6, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*IERR (/USB Camera Power Enable)*/
+ GLK_GPIO_PAD_CONF("GPIO_41", GPIO_41, M0, GPI, ACPI_D, NA,
+ NA, WAKE_ENABLED,P_20K_H,
+ NO_INVERT, GPIO_ROUT_SMI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*SOC_EXTSMI_N */
+ GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE1", GPIO_42, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE2", GPIO_43, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("USB_OC0_B", GPIO_44, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("USB_OC1_B", GPIO_45, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("DSI_I2C_SDA", GPIO_46, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("DSI_I2C_SCL", GPIO_47, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_I2C_SDA", GPIO_48, M1, NA, NA, NA, NA, NA, P_1K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */
+ GLK_GPIO_PAD_CONF("PMC_I2C_SCL", GPIO_49, M1, NA, NA, NA, NA, NA, P_1K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */
+ GLK_GPIO_PAD_CONF("LPSS_I2C0_SDA", GPIO_50, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C0 - Audio Codec */
+ GLK_GPIO_PAD_CONF("LPSS_I2C0_SCL", GPIO_51, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C0 - Audio Codec */
+ GLK_GPIO_PAD_CONF("LPSS_I2C1_SDA", GPIO_52, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C1 - NFC */
+ GLK_GPIO_PAD_CONF("LPSS_I2C1_SCL", GPIO_53, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C1 - NFC */
+ GLK_GPIO_PAD_CONF("LPSS_I2C2_SDA", GPIO_54, M0, HI_Z, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("LPSS_I2C2_SCL", GPIO_55, M0, HI_Z, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("LPSS_I2C3_SDA", GPIO_56, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */
+ GLK_GPIO_PAD_CONF("LPSS_I2C3_SCL", GPIO_57, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */
+ GLK_GPIO_PAD_CONF("LPSS_I2C4_SDA", GPIO_58, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/
+ GLK_GPIO_PAD_CONF("LPSS_I2C4_SCL", GPIO_59, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/
+ GLK_GPIO_PAD_CONF("LPSS_UART0_RXD", GPIO_60, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */
+ GLK_GPIO_PAD_CONF("LPSS_UART0_TXD", GPIO_61, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */
+ GLK_GPIO_PAD_CONF("LPSS_UART0_RTS_B", GPIO_62, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */
+ GLK_GPIO_PAD_CONF("LPSS_UART0_CTS_B", GPIO_63, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */
+#if 0
+ GLK_GPIO_PAD_CONF("LPSS_UART2_RXD", GPIO_64, M1, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART2 - DBG UART*/
+ GLK_GPIO_PAD_CONF("LPSS_UART2_TXD", GPIO_65, M1, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/*UART2 - DBG UART*/
+#endif
+ GLK_GPIO_PAD_CONF("LPSS_UART2_RTS_B", GPIO_66, M0, GPO, NA, HI,
+ NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/*RF_KILL_WWAN */
+ GLK_GPIO_PAD_CONF("LPSS_UART2_CTS_B", GPIO_67, M0, GPI, GPIO_D, NA,
+ LEVEL, WAKE_DISABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/*SPI TPM Interrupt */
+ GLK_GPIO_PAD_CONF("PMC_SPI_FS0", GPIO_68, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_SPI_FS1", GPIO_69, M0, GPI, ACPI_D, NA,
+ EDGE, WAKE_DISABLED, P_20K_L,
+ NO_INVERT, GPIO_ROUT_IOAPIC, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*SIM Detect*/
+ GLK_GPIO_PAD_CONF("PMC_SPI_FS2", GPIO_70, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_SPI_RXD", GPIO_71, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_SPI_TXD", GPIO_72, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_SPI_CLK", GPIO_73, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("THERMTRIP_B", GPIO_74, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PROCHOT_B", GPIO_75, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("EMMC_RST_B", GPIO_211, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("GPIO_212", GPIO_212, M0, GPI, ACPI_D, NA,
+ LEVEL, WAKE_ENABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*Touch Panel Interrupt*/
+ GLK_GPIO_PAD_CONF("GPIO_213", GPIO_213, M0, GPO, NA, HI, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*DNX LED - CSE owned*/
+ GLK_GPIO_PAD_CONF("GPIO_214", GPIO_214, M0, GPO, NA, HI, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*LAN Isolate*/
+
+/* NORTH COMMUNITY GPIOS */
+ GLK_GPIO_PAD_CONF("SVID0_ALERT_B", GPIO_76, M1, NA, NA , NA , NA , NA , P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /*SVID Alert*/
+ GLK_GPIO_PAD_CONF("SVID0_DATA", GPIO_77, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Data */
+ GLK_GPIO_PAD_CONF("SVID0_CLK", GPIO_78, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Clk */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_CLK", GPIO_79, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS0", GPIO_80, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor CS */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS1", GPIO_81, M3, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* FST_SPI_CS2_B - TPM */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_RXD", GPIO_82, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_TXD", GPIO_83, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_CLK", GPIO_84, M3, NA, NA, NA, NA, NA, P_NONE, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), /* SPI iTouch*/
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS0", GPIO_85, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch CS
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS1", GPIO_86, M3, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS2", GPIO_87, M3, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_RXD", GPIO_88, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_TXD", GPIO_89, M3, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch
+ GLK_GPIO_PAD_CONF("FST_SPI_CS0_B", GPIO_90, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI Boot Flash CS
+ GLK_GPIO_PAD_CONF("FST_SPI_CS1_B", GPIO_91, M0, HI_Z, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH),
+ GLK_GPIO_PAD_CONF("FST_SPI_MOSI_IO0", GPIO_92, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_MISO_IO1", GPIO_93,M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_IO2", GPIO_94, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_IO3", GPIO_95, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_CLK", GPIO_96, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_CLK_FB", GPIO_97, NA, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, LAST_VALUE, SAME, NA, GPIO_NORTH),
+ GLK_GPIO_PAD_CONF("PMU_PLTRST_B", GPIO_98, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PLTRST
+ GLK_GPIO_PAD_CONF("PMU_PWRBTN_B", GPIO_99, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PWRBTN
+ GLK_GPIO_PAD_CONF("PMU_SLP_S0_B", GPIO_100, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP
+ GLK_GPIO_PAD_CONF("PMU_SLP_S3_B", GPIO_101, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP
+ GLK_GPIO_PAD_CONF("PMU_SLP_S4_B", GPIO_102, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP
+ GLK_GPIO_PAD_CONF("SUSPWRDNACK", GPIO_103, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUSPWRDNAC
+ GLK_GPIO_PAD_CONF("EMMC_DNX_PWR_EN_B", GPIO_104, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: EMMC_DNX
+ GLK_GPIO_PAD_CONF("GPIO_105", GPIO_105, M0, GPO, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Reset
+ GLK_GPIO_PAD_CONF("PMU_BATLOW_B", GPIO_106, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_BATLOW
+ GLK_GPIO_PAD_CONF("PMU_RESETBUTTON_B", GPIO_107, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_RESETBUTTON
+ GLK_GPIO_PAD_CONF("PMU_SUSCLK", GPIO_108, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SUSCLK: WiFi/EC
+ GLK_GPIO_PAD_CONF("SUS_STAT_B", GPIO_109, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUS_STAT
+ GLK_GPIO_PAD_CONF("LPSS_I2C5_SDA", GPIO_110, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0
+ GLK_GPIO_PAD_CONF("LPSS_I2C5_SCL", GPIO_111, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0
+ GLK_GPIO_PAD_CONF("LPSS_I2C6_SDA", GPIO_112, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1
+ GLK_GPIO_PAD_CONF("LPSS_I2C6_SCL", GPIO_113, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1
+ GLK_GPIO_PAD_CONF("LPSS_I2C7_SDA", GPIO_114, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Tocuh panel
+ GLK_GPIO_PAD_CONF("LPSS_I2C7_SCL", GPIO_115, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Touch Panel
+ GLK_GPIO_PAD_CONF("PCIE_WAKE0_B", GPIO_116, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-1
+ GLK_GPIO_PAD_CONF("PCIE_WAKE1_B", GPIO_117, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - LAN
+ GLK_GPIO_PAD_CONF("PCIE_WAKE2_B", GPIO_118, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-2/PCIe M.2 WWAN
+ GLK_GPIO_PAD_CONF("PCIE_WAKE3_B", GPIO_119, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - M.2 WiFi
+ GLK_GPIO_PAD_CONF("PCIE_CLKREQ0_B", GPIO_120, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-1
+ GLK_GPIO_PAD_CONF("PCIE_CLKREQ1_B", GPIO_121, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - LAN
+ GLK_GPIO_PAD_CONF("PCIE_CLKREQ2_B", GPIO_122, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-2/PCIe M.2 WWAN
+ GLK_GPIO_PAD_CONF("PCIE_CLKREQ3_B", GPIO_123, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - M.2 WiFi
+ GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SDA", GPIO_124, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC
+ GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SCL", GPIO_125, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC
+ GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SDA", GPIO_126, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC
+ GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SCL", GPIO_127, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC
+ GLK_GPIO_PAD_CONF("PANEL0_VDDEN", GPIO_128, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH),//Function 1: PANEL0_VDDEN
+ GLK_GPIO_PAD_CONF("PANEL0_BKLTEN", GPIO_129, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTEN
+ GLK_GPIO_PAD_CONF("PANEL0_BKLTCTL", GPIO_130, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTCTL
+ GLK_GPIO_PAD_CONF("HV_DDI0_HPD", GPIO_131, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI0 HPD
+ GLK_GPIO_PAD_CONF("HV_DDI1_HPD", GPIO_132, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI1 HPD
+ GLK_GPIO_PAD_CONF("HV_EDP_HPD", GPIO_133, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: eDP HPD
+ GLK_GPIO_PAD_CONF("GPIO_134", GPIO_134, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-1 Power Enable
+ GLK_GPIO_PAD_CONF("GPIO_135", GPIO_135, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Power Enable
+ GLK_GPIO_PAD_CONF("GPIO_136", GPIO_136, M0, GPO, NA, LO, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //DGPU Power Select
+ GLK_GPIO_PAD_CONF("GPIO_137", GPIO_137, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 slot-1 Reset
+ GLK_GPIO_PAD_CONF("GPIO_138",GPIO_138, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 5: SATA_GP0 (DC RTD3 need)
+ GLK_GPIO_PAD_CONF("GPIO_139", GPIO_139, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, LAST_VALUE, DISPUPD, NA, GPIO_NORTH), //Function 5: SATA_GP1 (ZPODD_DEV_DET)
+ GLK_GPIO_PAD_CONF("GPIO_140", GPIO_140, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP0 (DC DEV SLP)
+ GLK_GPIO_PAD_CONF("GPIO_141", GPIO_141, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP1 (ZPODD DEV ATN)
+ GLK_GPIO_PAD_CONF("GPIO_142", GPIO_142, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_LED
+ GLK_GPIO_PAD_CONF("GPIO_143", GPIO_143, M0, GPI, ACPI_D, NA, LEVEL, WAKE_DISABLED, P_20K_L,
+ NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, SAME, NA, GPIO_NORTH), //DGPU Power Ok
+ GLK_GPIO_PAD_CONF("GPIO_144", GPIO_144, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_VDDEN
+ GLK_GPIO_PAD_CONF("GPIO_145", GPIO_145, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTEN
+ GLK_GPIO_PAD_CONF("GPIO_146", GPIO_146, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTCTL
+ GLK_GPIO_PAD_CONF("LPC_ILB_SERIRQ", GPIO_147, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 1:LPC_ILB_SERIRQ
+ GLK_GPIO_PAD_CONF("LPC_CLKOUT0", GPIO_148, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - EC
+ GLK_GPIO_PAD_CONF("LPC_CLKOUT1", GPIO_149, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - dTPM
+ GLK_GPIO_PAD_CONF("LPC_AD0", GPIO_150, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD0
+ GLK_GPIO_PAD_CONF("LPC_AD1", GPIO_151, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD1
+ GLK_GPIO_PAD_CONF("LPC_AD2", GPIO_152, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD2
+ GLK_GPIO_PAD_CONF("LPC_AD3", GPIO_153, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD3
+ GLK_GPIO_PAD_CONF("LPC_CLKRUNB", GPIO_154, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1: LPC_CLKRUNB
+ GLK_GPIO_PAD_CONF("LPC_FRAMEB", GPIO_155, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_FRAMEB
+
+/* AUDIO COMMUNITY GPIOS*/
+
+ GLK_GPIO_PAD_CONF("AVS_I2S0_BCLK", GPIO_157, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN_Reset/dGPS Reset; Output
+ GLK_GPIO_PAD_CONF("AVS_I2S0_WS_SYNC", GPIO_158, M0, GPO, NA, LO, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //NFC_DFU
+ GLK_GPIO_PAD_CONF("AVS_I2S0_SDI", GPIO_159, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT , NA, TXDRXE, ENPD, NA, GPIO_AUDIO),//NFC Reset - module has PU to 3.3V
+ GLK_GPIO_PAD_CONF("AVS_I2S0_SDO", GPIO_160, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //MDSI_Reset
+ GLK_GPIO_PAD_CONF("AVS_I2S1_MCLK", GPIO_161, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //Touch panel Reset
+ GLK_GPIO_PAD_CONF("AVS_I2S1_BCLK", GPIO_162, M0, GPI, NA, HI, NA, WAKE_DISABLED, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO),
+ GLK_GPIO_PAD_CONF("AVS_I2S1_WS_SYNC", GPIO_163, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //M.2 WiFi Reset
+ GLK_GPIO_PAD_CONF("AVS_I2S1_SDI", GPIO_164, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, TXDRXE, ENPD, NA, GPIO_AUDIO), //Touch Panel Power Enable
+ GLK_GPIO_PAD_CONF("AVS_I2S1_SDO", GPIO_165, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN PWR EN/Full card power off
+ GLK_GPIO_PAD_CONF("AVS_HDA_BCLK", GPIO_166, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_HDA_WS_SYNC", GPIO_167, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_HDA_SDI", GPIO_168, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_HDA_SDO", GPIO_169, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_HDA_RSTB", GPIO_170, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_M_CLK_A1", GPIO_171, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC
+ GLK_GPIO_PAD_CONF("AVS_M_CLK_B1", GPIO_172, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC
+ GLK_GPIO_PAD_CONF("AVS_M_DATA_1", GPIO_173, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC
+ GLK_GPIO_PAD_CONF("AVS_M_CLK_AB2", GPIO_174, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Funciton 1: DMIC
+ GLK_GPIO_PAD_CONF("AVS_M_DATA_2", GPIO_175, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC
+
+/* SCC COMMUNITY GPIOS */
+
+ GLK_GPIO_PAD_CONF("SMB_ALERTB", GPIO_176, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB
+ GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB
+ GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB
+ GLK_GPIO_PAD_CONF("SDCARD_LVL_WP", GPIO_187, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_CLK", GPIO_179, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_CLK_FB", GPIO_180, NA, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("SDCARD_D0", GPIO_181, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_D1", GPIO_182, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_D2", GPIO_183, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_D3", GPIO_184, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_CMD", GPIO_185, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_CD_B", GPIO_186, M0, GPI, GPIO_D, NA, EDGE, NA, P_20K_H,
+ NO_INVERT, NA, TXDRXE, NA, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_PWR_DOWN_B", GPIO_188, M0, GPO, NA, LO, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("GPIO_210", GPIO_210, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("OSC_CLK_OUT_0", GPIO_189, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("OSC_CLK_OUT_1", GPIO_190, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("CNV_BRI_DT", GPIO_191, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("CNV_BRI_RSP", GPIO_192, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("CNV_RGI_DT", GPIO_193, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("CNV_RGI_RSP", GPIO_194, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("CNV_RF_RESET_B", GPIO_195, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("XTAL_CLKREQ", GPIO_196, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("SDIO_CLK_FB", GPIO_197, M2, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("EMMC0_CLK", GPIO_198, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_CLK_FB", GPIO_199, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("EMMC0_D0", GPIO_200, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D1", GPIO_201, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D2", GPIO_202, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D3", GPIO_203, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D4", GPIO_204, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D5", GPIO_205, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D6", GPIO_206, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D7", GPIO_207, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_CMD", GPIO_208, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_STROBE", GPIO_209, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC
};
const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
@@ -33,6 +479,12 @@ const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
+ GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA,
+ WAKE_DISABLED, P_20K_H,
+ NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD
+ GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA,
+ WAKE_DISABLED, P_20K_H,
+ NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD
};
const struct pad_config * __attribute__((weak))
@@ -44,6 +496,7 @@ variant_early_gpio_table(size_t *num)
/* GPIO settings before entering sleep. */
static const struct pad_config sleep_gpio_table[] = {
+/* TODO */
};
const struct pad_config * __attribute__((weak))
@@ -54,8 +507,7 @@ variant_sleep_gpio_table(size_t *num)
}
static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
- CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
+/* TODO */
};
const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
index f60bfdc..e5ed830 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
@@ -18,22 +18,12 @@
#include <soc/gpio.h>
-/*
- * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
- * which is North community
- */
-#define EC_SCI_GPI GPE0_DW1_11
+#define EC_SCI_GPI 0x25 /*GPIO_37*/
/* EC SMI */
#define EC_SMI_GPI GPIO_49
-/*
- * On lidopen/lidclose GPIO_22 from North Community gets toggled and
- * is used in _PRW to wake up device from sleep. GPIO_22 maps to
- * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
- * EDGE_SINGLE and INVERT.
- */
-#define GPE_EC_WAKE GPE0_DW1_22
+#define GPE_EC_WAKE 0x26 /*GPIO_38*/
/* Write Protect and indication if EC is in RW code. */
#define GPIO_PCH_WP GPIO_75
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