[coreboot-gerrit] New patch to review for coreboot: riscv: Add support for timer interrupts

[Ronald G. Minnich (rminnich@gmail.com)]

Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17807

-gerrit

commit 89eedeca495e13118242019254c55a0aa71d6779
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Mon Dec 12 15:09:42 2016 -0800

    riscv: Add support for timer interrupts
    
    RISCV requires that timer interrupts be handled in machine
    mode and delegated as necessary. Also you can only reset the
    timer interrupt by writing to mtimecmp. Further, you must
    write a number > mtime, not just != mtime. This rather clumsy
    situation requires that we write some value into the future
    into mtimecmp lest we never be able to leave machine mode as
    the interrupt either is not cleared or instantly reoccurs.
    
    This current code is tested and works for harvey (Plan 9)
    timer interrupts.
    
    Change-Id: I8538d5fd8d80d9347773c638f5cbf0da18dc1cae
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
 src/arch/riscv/trap_handler.c   | 68 ++++++++++++++++++++++++++++++++++++++++-
 src/arch/riscv/virtual_memory.c |  6 ++--
 2 files changed, 71 insertions(+), 3 deletions(-)

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index c7a11c6..ec11c06 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -20,6 +20,10 @@
 #include <mcall.h>
 #include <string.h>
 #include <vm.h>
+#include <commonlib/configstring.h>
+
+static uint64_t *time;
+static uint64_t *timecmp;
 
 void handle_supervisor_call(trapframe *tf) {
 	uintptr_t call = tf->gpr[17]; /* a7 */
@@ -130,8 +134,67 @@ static void print_trap_information(const trapframe *tf)
 	printk(BIOS_DEBUG, "Stored sp:          %p\n", (void*) tf->gpr[2]);
 }
 
-void trap_handler(trapframe *tf) {
+static void gettimer(void)
+{
+	query_result res;
+	const char *config;
+
+	config = configstring();
+	query_rtc(config, (uintptr_t *)&time);
+	if (!time)
+		die("Got timer interrupt but found no timer.");
+	res = query_config_string(config, "core{0{0{timecmp");
+	timecmp = (void *)get_uint(res);
+	if (!timecmp)
+		die("Got a timer interrupt but found no timecmp.");
+}
+
+static void interrupt_handler(trapframe *tf)
+{
+	uint64_t cause = tf->cause & ~0x8000000000000000ULL;
+	uint32_t c;
+
+	switch (cause) {
+	case 7:
+		// The only way to reset the timer interrupt is to
+		// write mtimecmp. But we also have to ensure the
+		// comparison fails, for a long time, to let
+		// supervisor interrupt handler compute a new value
+		// and set it. Finally, it fires if mtimecmp is <=
+		// mtime, not =, so setting mtimecmp to 0 won't work
+		// to clear the interrupt and disable a new one. We
+		// have to set the mtimecmp far into the future.
+		// Akward!
+		//
+		// Further, maybe the platform doesn't have the
+		// hardware or the payload never uses it. We hold off
+		// querying some things until we are sure we need
+		// them. What to do if we can not find them? There are
+		// no good options.
+		if (!timecmp)
+			gettimer();
+		*timecmp = *time + 0x10000;
+		c = read_csr(mip);
+		c |= MIP_STIP;
+		c &= ~MIP_MTIP;
+		write_csr(sip, c);
+		break;
+	default:
+		printk(BIOS_EMERG, "======================================\n");
+		printk(BIOS_EMERG, "Coreboot: can not interrupt: 0x%llx\n",
+		       cause);
+		printk(BIOS_EMERG, "======================================\n");
+		print_trap_information(tf);
+		break;
+	}
+}
+void trap_handler(trapframe *tf)
+{
 	write_csr(mscratch, tf);
+	if (tf->cause & 0x8000000000000000ULL) {
+		interrupt_handler(tf);
+		return;
+	}
 
 	switch(tf->cause) {
 		case CAUSE_MISALIGNED_FETCH:
@@ -159,6 +222,9 @@ void trap_handler(trapframe *tf) {
 			handle_supervisor_call(tf);
 			break;
 		default:
+			printk(BIOS_EMERG, "================================\n");
+			printk(BIOS_EMERG, "Coreboot: can not handle a trap:\n");
+			printk(BIOS_EMERG, "================================\n");
 			print_trap_information(tf);
 			break;
 	}
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 26a0169..8ee3ece 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -292,12 +292,14 @@ void initVirtualMemory(void) {
 void mstatus_init(void)
 {
 	uintptr_t ms = 0;
+	uintptr_t ints = MIP_STIP | MIP_SSIP;
 	ms = INSERT_FIELD(ms, MSTATUS_FS, 3);
 	ms = INSERT_FIELD(ms, MSTATUS_XS, 3);
 	write_csr(mstatus, ms);
 
-	clear_csr(mip, MIP_MSIP);
-	set_csr(mie, MIP_MSIP);
+	clear_csr(mip, ints);
+	set_csr(mie, MIP_MTIP | ints);
+	set_csr(mideleg, ints);
 
 	set_csr(medeleg, delegate);