[coreboot-gerrit] New patch to review for coreboot: mainboard/google/reef: set SLP_S3_L assertion width to 50ms

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16327

-gerrit

commit 9c6c0c94504dd42a5ddc92491408ca74628715cc
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Aug 25 15:44:39 2016 -0500

    mainboard/google/reef: set SLP_S3_L assertion width to 50ms
    
    The reef board needs at least ~30ms for its S0 rails to discharge
    when S3 is entered. The 50ms setting is the closest to meet those
    needs so use that setting to ensure the S0 rails fully discharge.
    
    BUG=chrome-os-partner:56581
    
    Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/reef/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index a877e86..4605276 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -50,6 +50,9 @@ chip soc/intel/apollolake
 	# Enable I2C2 bus early for TPM access
 	register "i2c[2].early_init" = "1"
 
+	# Minimum SLP S3 assertion width
+	register "slp_s3_assertion_width" = "SLP_S3_ASSERT_50_MSEC"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 on  end	# - DPTF