[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: add option for SLP_S3_L assertion width

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16326

-gerrit

commit 850bd5160ef060e49158a8ae5199a70b1c4ae261
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Aug 25 15:42:04 2016 -0500

    soc/intel/apollolake: add option for SLP_S3_L assertion width
    
    In order to provide time for the S0 rails to discharge one needs
    to be able to set the SLP_S3_L assertion width. The default is
    60 microcseconds which is not slow enough on most boards. Therefore
    provide a devicetree option for the mainboard to set accordingly
    for its needs.
    
    BUG=chrome-os-partner:56581
    
    Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/apollolake/chip.h           |  3 +++
 src/soc/intel/apollolake/include/soc/pm.h |  6 +++++
 src/soc/intel/apollolake/pmc.c            | 40 +++++++++++++++++++++++++++++++
 3 files changed, 49 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 16c3aeb..fd5d161 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -106,6 +106,9 @@ struct soc_intel_apollolake_config {
 
 	/* Enable DPTF support */
 	int dptf_enable;
+
+	/* SLP S3 minimum assertion width. */
+	int slp_s3_assertion_width;
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 5641e54..f17ed54 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -129,6 +129,12 @@
 #define GEN_PMCON2		0x1024
 #       define RPS		(1 <<  2)
 #define GEN_PMCON3		0x1028
+#       define SLP_S3_ASSERT_WIDTH_SHIFT	10
+#       define SLP_S3_ASSERT_MASK	(0x3 << SLP_S3_ASSERT_WIDTH_SHIFT)
+#       define SLP_S3_ASSERT_60_USEC	0x0
+#       define SLP_S3_ASSERT_1_MSEC	0x1
+#       define SLP_S3_ASSERT_50_MSEC	0x2
+#       define SLP_S3_ASSERT_2_SEC	0x3
 #define ETR			0x1048
 #       define CF9_LOCK         (1 << 31)
 #       define CF9_GLB_RST      (1 << 20)
diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c
index 92a150d..60bf27e 100644
--- a/src/soc/intel/apollolake/pmc.c
+++ b/src/soc/intel/apollolake/pmc.c
@@ -25,6 +25,7 @@
 #include <soc/gpio.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
+#include <timer.h>
 #include "chip.h"
 
 /*
@@ -132,11 +133,50 @@ static void pch_set_acpi_mode(void)
 	}
 }
 
+static void set_slp_s3_assertion_width(int width)
+{
+	int time_usec;
+	uint32_t reg;
+	uintptr_t gen_pmcon3 = get_pmc_mmio_bar() + GEN_PMCON3;
+
+	switch (width) {
+	case SLP_S3_ASSERT_60_USEC:
+		time_usec = 60;
+		break;
+	case SLP_S3_ASSERT_1_MSEC:
+		time_usec = 1 * USECS_PER_MSEC;
+		break;
+	case SLP_S3_ASSERT_50_MSEC:
+		time_usec = 50 * USECS_PER_MSEC;
+		break;
+	case SLP_S3_ASSERT_2_SEC:
+		time_usec = 2 * USECS_PER_SEC;
+		break;
+	default:
+		/* Default to most conservative. */
+		width = SLP_S3_ASSERT_2_SEC;
+		time_usec = 2 * USECS_PER_SEC;
+		break;
+	}
+
+	printk(BIOS_DEBUG, "SLP S3 assertion width: %d usecs\n", time_usec);
+
+	reg = read32((void *)gen_pmcon3);
+	reg &= ~SLP_S3_ASSERT_MASK;
+	reg |= width << SLP_S3_ASSERT_WIDTH_SHIFT;
+	write32((void *)gen_pmcon3, reg);
+}
+
 static void pmc_init(struct device *dev)
 {
+	const struct soc_intel_apollolake_config *cfg = dev->chip_info;
+
 	/* Set up GPE configuration */
 	pmc_gpe_init();
 	pch_set_acpi_mode();
+
+	if (cfg != NULL)
+		set_slp_s3_assertion_width(cfg->slp_s3_assertion_width);
 }
 
 static const struct device_operations device_ops = {