[coreboot-gerrit] New patch to review for coreboot: src/cpu: Capitalize CPU, ACPI and APIC
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Sun Aug 21 10:30:22 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16276
-gerrit
commit baf49ad861dcc7237166d6c24e66c488c64c918d
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Sun Aug 21 10:12:15 2016 +0200
src/cpu: Capitalize CPU, ACPI and APIC
Change-Id: I82e0736dc6b44cfcc57cdfdc786c85c4b6882260
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/cpu/allwinner/a10/clock.h | 2 +-
src/cpu/amd/agesa/family10/model_10_init.c | 2 +-
src/cpu/amd/agesa/family12/model_12_init.c | 2 +-
src/cpu/amd/agesa/family14/model_14_init.c | 2 +-
src/cpu/amd/agesa/family15/model_15_init.c | 2 +-
src/cpu/amd/agesa/family15rl/model_15_init.c | 2 +-
src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +-
src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +-
src/cpu/amd/dualcore/amd_sibling.c | 8 ++++----
src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 +-
src/cpu/amd/family_10h-family_15h/model_10xxx_init.c | 2 +-
src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +-
src/cpu/amd/geode_lx/geode_lx_init.c | 2 +-
src/cpu/amd/model_fxx/init_cpus.c | 6 +++---
src/cpu/amd/model_fxx/model_fxx_init.c | 2 +-
src/cpu/amd/pi/00630F01/model_15_init.c | 2 +-
src/cpu/amd/pi/00660F01/model_15_init.c | 2 +-
src/cpu/amd/pi/00730F01/model_16_init.c | 2 +-
src/cpu/amd/quadcore/amd_sibling.c | 8 ++++----
src/cpu/intel/car/cache_as_ram_ht.inc | 2 +-
src/cpu/intel/ep80579/ep80579_init.c | 2 +-
src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 2 +-
src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 2 +-
src/cpu/intel/haswell/haswell_init.c | 2 +-
src/cpu/intel/model_1067x/model_1067x_init.c | 4 ++--
src/cpu/intel/model_106cx/model_106cx_init.c | 2 +-
src/cpu/intel/model_2065x/model_2065x_init.c | 2 +-
src/cpu/intel/model_206ax/model_206ax_init.c | 2 +-
src/cpu/intel/model_65x/model_65x_init.c | 2 +-
src/cpu/intel/model_67x/model_67x_init.c | 2 +-
src/cpu/intel/model_68x/model_68x_init.c | 2 +-
src/cpu/intel/model_69x/model_69x_init.c | 2 +-
src/cpu/intel/model_6bx/model_6bx_init.c | 2 +-
src/cpu/intel/model_6dx/model_6dx_init.c | 2 +-
src/cpu/intel/model_6ex/model_6ex_init.c | 2 +-
src/cpu/intel/model_6fx/model_6fx_init.c | 2 +-
src/cpu/intel/model_6xx/model_6xx_init.c | 2 +-
src/cpu/intel/model_f0x/model_f0x_init.c | 2 +-
src/cpu/intel/model_f1x/model_f1x_init.c | 2 +-
src/cpu/intel/model_f2x/model_f2x_init.c | 2 +-
src/cpu/intel/model_f3x/model_f3x_init.c | 2 +-
src/cpu/intel/model_f4x/model_f4x_init.c | 2 +-
src/cpu/intel/speedstep/speedstep.c | 2 +-
src/cpu/via/c3/c3_init.c | 2 +-
src/cpu/via/c7/c7_init.c | 2 +-
src/cpu/via/nano/nano_init.c | 2 +-
src/cpu/x86/16bit/entry16.inc | 2 +-
src/cpu/x86/Kconfig | 2 +-
src/cpu/x86/lapic/apic_timer.c | 2 +-
src/cpu/x86/lapic/lapic.c | 8 ++++----
src/cpu/x86/lapic/lapic_cpu_init.c | 4 ++--
src/cpu/x86/mp_init.c | 14 +++++++-------
src/cpu/x86/smm/smm_module_loader.c | 2 +-
src/cpu/x86/smm/smmrelocate.S | 2 +-
54 files changed, 73 insertions(+), 73 deletions(-)
diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h
index d1729a3..a723ecc 100644
--- a/src/cpu/allwinner/a10/clock.h
+++ b/src/cpu/allwinner/a10/clock.h
@@ -212,7 +212,7 @@ struct a10_ccm {
u8 res3[0xc];
u32 pll_lock_dbg; /* 0x4c pll lock time debug */
u32 osc24m_cfg; /* 0x50 osc24m control */
- u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */
+ u32 cpu_ahb_apb0_cfg; /* 0x54 CPU, ahb and apb0 divide ratio */
u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */
u32 axi_gate; /* 0x5c axi module clock gating */
u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c
index 22a92e1..ef70725 100644
--- a/src/cpu/amd/agesa/family10/model_10_init.c
+++ b/src/cpu/amd/agesa/family10/model_10_init.c
@@ -57,7 +57,7 @@ static void model_10_init(device_t dev)
enable_cache();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Set the processor name string */
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index a0b9479..2fc943c 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -62,7 +62,7 @@ static void model_12_init(device_t dev)
enable_cache();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Set the processor name string */
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 84ce755..5e8c9de 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -82,7 +82,7 @@ static void model_14_init(device_t dev)
wrmsr(MCI_STATUS + (i * 4), msr);
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c
index 525959f..7df9153 100644
--- a/src/cpu/amd/agesa/family15/model_15_init.c
+++ b/src/cpu/amd/agesa/family15/model_15_init.c
@@ -67,7 +67,7 @@ static void model_15_init(device_t dev)
wrmsr(MCI_STATUS + (i * 4), msr);
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c
index 0492be3..b28ad57 100644
--- a/src/cpu/amd/agesa/family15rl/model_15_init.c
+++ b/src/cpu/amd/agesa/family15rl/model_15_init.c
@@ -81,7 +81,7 @@ static void model_15_init(device_t dev)
wrmsr(MCI_STATUS + (i * 4), msr);
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 27aedaf..5153a8b 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -80,7 +80,7 @@ static void model_15_init(device_t dev)
wrmsr(MCI_STATUS + (i * 4), msr);
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 3d3afec..f62e698 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -79,7 +79,7 @@ static void model_16_init(device_t dev)
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index e0723ce..429cc35 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -82,7 +82,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
siblings = get_max_siblings(nodes);
- if(bsp_apic_id > 0) { // io apic could start from 0
+ if (bsp_apic_id > 0) { // io APIC could start from 0
return 0;
} else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
return 1;
@@ -108,8 +108,8 @@ unsigned get_apicid_base(unsigned ioapic_num)
if((!disable_siblings) && (siblings>0) ) {
/* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel
- and the kernel will try to get one that is small than 16 to make io apic work.
- I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */
+ and the kernel will try to get one that is small than 16 to make io APIC work.
+ I don't know when the kernel can support 256 APIC id. (APIC_EXT_ID is enabled) */
//4:10 for two way 8:12 for four way 16:16 for eight way
//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
@@ -122,7 +122,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
- printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
+ printk(BIOS_INFO, "if the IO APIC device doesn't support 256 APIC id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
enable_apic_ext_id(nodes);
}
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index 6fefc3b..4405e3c 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -419,7 +419,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
if (initial_apicid != 0) // other than bsp
#endif
{
- /* use initial apic id to lift it */
+ /* use initial APIC id to lift it */
u32 dword = lapic_read(LAPIC_ID);
dword &= ~(0xff << 24);
dword |=
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index a41374d..f8e6a27 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -133,7 +133,7 @@ static void model_10xxx_init(device_t dev)
enable_cache();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Set the processor name string */
diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c
index b6bad4d..531a362 100644
--- a/src/cpu/amd/geode_gx2/geode_gx2_init.c
+++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c
@@ -22,7 +22,7 @@ static void geode_gx2_init(device_t dev)
/* Turn on caching if we haven't already */
x86_enable_cache();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
//setup_lapic();
vsm_end_post_smi();
diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c
index 335caa3..8ff5848 100644
--- a/src/cpu/amd/geode_lx/geode_lx_init.c
+++ b/src/cpu/amd/geode_lx/geode_lx_init.c
@@ -40,7 +40,7 @@ static void geode_lx_init(device_t dev)
/* Turn on caching if we haven't already */
x86_enable_cache();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
//setup_lapic();
// do VSA late init
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 2ea4fb9..63c8823 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -54,7 +54,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
j = ((pci_read_config32(PCI_DEV(0, 0x18 + i, 3), 0xe8) >> 12) &
3);
if (nb_cfg_54) {
- if (j == 0) { // if it is single core, we need to increase siblings for apic calculation
+ if (j == 0) { // if it is single core, we need to increase siblings for APIC calculation
#if !CONFIG_K8_REV_F_SUPPORT
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
@@ -266,7 +266,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
if (initial_apicid != 0) // other than bsp
#endif
{
- /* use initial apic id to lift it */
+ /* use initial APIC id to lift it */
u32 dword = lapic_read(LAPIC_ID);
dword &= ~(0xff << 24);
dword |=
@@ -300,7 +300,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
if (id.coreid == 0) {
distinguish_cpu_resets(id.nodeid);
-// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set
+// start_other_core(id.nodeid); // start second core in first CPU, only allowed for nb_cfg_54 is not set
}
//here don't need to wait
lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the CPU is started
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index e22eae4..3d69dcb 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -508,7 +508,7 @@ static void model_fxx_init(device_t dev)
/* Set the processor name string */
init_processor_name();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 7c4d171..afbade4 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -79,7 +79,7 @@ static void model_15_init(device_t dev)
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index de7ee38..e252c3d 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -94,7 +94,7 @@ static void model_15_init(device_t dev)
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 6cb3009..a9751a2 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -77,7 +77,7 @@ static void model_16_init(device_t dev)
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
#if CONFIG_LOGICAL_CPUS
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index 397a3dd..c1e243a 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -82,7 +82,7 @@ u32 get_apicid_base(u32 ioapic_num)
siblings = get_max_siblings(sysconf.nodes);
- if(sysconf.bsp_apicid > 0) { // io apic could start from 0
+ if(sysconf.bsp_apicid > 0) { // io APIC could start from 0
return 0;
} else if (sysconf.enabled_apic_ext_id) { // enabled ext id but bsp = 0
return 1;
@@ -96,8 +96,8 @@ u32 get_apicid_base(u32 ioapic_num)
if((!disable_siblings) && (siblings>0) ) {
/* for 8 way dual core, we will used up apicid 16:16, actually
16 is not allowed by current kernel and the kernel will try
- to get one that is small than 16 to make io apic work. I don't
- know when the kernel can support 256 apic id.
+ to get one that is small than 16 to make io APIC work. I don't
+ know when the kernel can support 256 APIC id.
(APIC_EXT_ID is enabled) */
//4:10 for two way 8:12 for four way 16:16 for eight way
@@ -110,7 +110,7 @@ u32 get_apicid_base(u32 ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
- printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n");
+ printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 APIC id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n");
enable_apic_ext_id(sysconf.nodes);
}
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 0ec2a9d..3e2b3e2 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -87,7 +87,7 @@ addrsize_no_MSR:
movl $0x0f, %edx
/* Preload high word of address mask (in %edx) for Variable
- * MTRRs 0 and 1 and enable local apic at default base.
+ * MTRRs 0 and 1 and enable local APIC at default base.
*/
addrsize_set_high:
xorl %eax, %eax
diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c
index 3093975..78860b4 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -34,7 +34,7 @@ static void ep80579_init(struct device *dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
};
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
index 1d4ae58..6789bae 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
@@ -386,7 +386,7 @@ static void model_206ax_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
index badadf1..ef48c03 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
@@ -182,7 +182,7 @@ static void model_406dx_init(struct device *cpu)
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Enable virtualization */
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 799b66c..2fac879 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -720,7 +720,7 @@ static void haswell_init(struct device *cpu)
/* Clear out pending MCEs */
configure_mca();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 1812084..e28a331 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -32,7 +32,7 @@
static void init_timer(void)
{
- /* Set the apic timer to no interrupts and periodic mode */
+ /* Set the APIC timer to no interrupts and periodic mode */
lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
/* Set the divider to 1, no divider */
@@ -322,7 +322,7 @@ static void model_1067x_init(struct device *cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Initialize the APIC timer */
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index ac4606b..7f4a9ab 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -124,7 +124,7 @@ static void model_106cx_init(struct device *cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Enable virtualization */
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index 6bd20ba..7987f8e 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -379,7 +379,7 @@ static void model_2065x_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index a2cbfbf..e7bfd9e 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -572,7 +572,7 @@ static void model_206ax_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c
index 14da632..a4e222d 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -36,7 +36,7 @@ static void model_65x_init(struct device *dev)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
};
diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c
index d7c22fc..f4b8155 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -40,7 +40,7 @@ static void model_67x_init(struct device *cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
}
diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c
index e276791..ad1f3a0 100644
--- a/src/cpu/intel/model_68x/model_68x_init.c
+++ b/src/cpu/intel/model_68x/model_68x_init.c
@@ -44,7 +44,7 @@ static void model_68x_init(struct device *cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
}
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index d283722..2f12224 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -18,7 +18,7 @@ static void model_69x_init(struct device *dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
};
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c
index 36da288..e52bd31 100644
--- a/src/cpu/intel/model_6bx/model_6bx_init.c
+++ b/src/cpu/intel/model_6bx/model_6bx_init.c
@@ -44,7 +44,7 @@ static void model_6bx_init(struct device *cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
}
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 73f71d8..a18b00c 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -31,7 +31,7 @@ static void model_6dx_init(struct device *dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
};
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index bc926a8..91633ec 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -154,7 +154,7 @@ static void model_6ex_init(struct device *cpu)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Enable virtualization */
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 30542e6..18160ad 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -177,7 +177,7 @@ static void model_6fx_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Enable virtualization */
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 102af74..68c0136 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -31,7 +31,7 @@ static void model_6xx_init(struct device *dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
};
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index 1eb234f..f833a56 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -31,7 +31,7 @@ static void model_f0x_init(struct device *dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
};
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index 77f442f..4af3934 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -31,7 +31,7 @@ static void model_f1x_init(struct device *dev)
/* Update the microcode */
intel_update_microcode_from_cbfs();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
};
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index 092afa0..97c7d9d 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -36,7 +36,7 @@ static void model_f2x_init(struct device *cpu)
intel_update_microcode_from_cbfs();
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Start up my CPU siblings */
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index 36ca5a6..8fbcaa7 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -36,7 +36,7 @@ static void model_f3x_init(struct device *cpu)
intel_update_microcode_from_cbfs();
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Start up my CPU siblings */
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index 7d198b3..c904b62 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -36,7 +36,7 @@ static void model_f4x_init(struct device *cpu)
intel_update_microcode_from_cbfs();
}
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
/* Start up my CPU siblings */
diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c
index 3ab3231..96ac8e5 100644
--- a/src/cpu/intel/speedstep/speedstep.c
+++ b/src/cpu/intel/speedstep/speedstep.c
@@ -110,7 +110,7 @@ static void speedstep_get_limits(sst_params_t *const params)
* @brief Generate full p-states table from processor parameters
*
* This is generic code and should work at least for Merom and Penryn
- * processors. It is used to generate acpi tables and configure EMTTM.
+ * processors. It is used to generate ACPI tables and configure EMTTM.
*/
void speedstep_gen_pstates(sst_table_t *const table)
{
diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c
index c28766e..e51c0d6 100644
--- a/src/cpu/via/c3/c3_init.c
+++ b/src/cpu/via/c3/c3_init.c
@@ -27,7 +27,7 @@ static void c3_init(struct device *dev)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
};
diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c
index e7c9fac..8ddc931 100644
--- a/src/cpu/via/c7/c7_init.c
+++ b/src/cpu/via/c7/c7_init.c
@@ -200,7 +200,7 @@ static void c7_init(struct device *dev)
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
};
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
index cdf0589..e84ef28 100644
--- a/src/cpu/via/nano/nano_init.c
+++ b/src/cpu/via/nano/nano_init.c
@@ -180,7 +180,7 @@ static void nano_init(struct device *dev)
/* Set up Memory Type Range Registers */
x86_setup_mtrrs();
x86_mtrr_check();
- /* Enable the local CPU apics */
+ /* Enable the local CPU APICs */
setup_lapic();
}
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index b4db834..cf366e0 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -79,7 +79,7 @@ _start16bit:
*
* The criteria for relocation have been relaxed to their
* utmost, so that we can use the same code for both
- * our initial entry point and startup of the second cpu.
+ * our initial entry point and startup of the second CPU.
* The code assumes when executing at _start16bit that:
* (((cs & 0xfff) == 0) and (ip == _start16bit & 0xffff))
* or
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index c4507bc..3e56d72 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -25,7 +25,7 @@ config LAPIC_MONOTONIC_TIMER
depends on UDELAY_LAPIC
select HAVE_MONOTONIC_TIMER
help
- Expose monotonic time using the local apic.
+ Expose monotonic time using the local APIC.
config UDELAY_LAPIC_FIXED_FSB
int
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index b16521a..41edde9 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -83,7 +83,7 @@ static inline u32 get_timer_fsb(void)
void init_timer(void)
{
- /* Set the apic timer to no interrupts and periodic mode */
+ /* Set the APIC timer to no interrupts and periodic mode */
lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED));
/* Set the divider to 1, no divider */
diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c
index 83a45b0..f6cbe17 100644
--- a/src/cpu/x86/lapic/lapic.c
+++ b/src/cpu/x86/lapic/lapic.c
@@ -17,9 +17,9 @@ void setup_lapic(void)
/* Only Pentium Pro and later have those MSR stuff */
msr_t msr;
- printk(BIOS_INFO, "Setting up local apic...");
+ printk(BIOS_INFO, "Setting up local APIC...");
- /* Enable the local apic */
+ /* Enable the local APIC */
msr = rdmsr(LAPIC_BASE_MSR);
msr.lo |= LAPIC_BASE_MSR_ENABLE;
msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
@@ -32,7 +32,7 @@ void setup_lapic(void)
lapic_write_around(LAPIC_TASKPRI,
lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
- /* Put the local apic in virtual wire mode */
+ /* Put the local APIC in virtual wire mode */
lapic_write_around(LAPIC_SPIV,
(lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK))
| LAPIC_SPIV_ENABLE);
@@ -61,7 +61,7 @@ void setup_lapic(void)
/* Only Pentium Pro and later have those MSR stuff */
msr_t msr;
- printk(BIOS_INFO, "Disabling local apic...");
+ printk(BIOS_INFO, "Disabling local APIC...");
msr = rdmsr(LAPIC_BASE_MSR);
msr.lo &= ~LAPIC_BASE_MSR_ENABLE;
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index aaeceef..792ae7a 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -165,7 +165,7 @@ static int lapic_start_cpu(unsigned long apicid)
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
- printk(BIOS_ERR, "CPU %ld: Second apic write timed out. "
+ printk(BIOS_ERR, "CPU %ld: Second APIC write timed out. "
"Disabling\n", apicid);
// too bad.
return 0;
@@ -546,7 +546,7 @@ void initialize_cpus(struct bus *cpu_bus)
info = cpu_info();
#if NEED_LAPIC == 1
- /* Ensure the local apic is enabled */
+ /* Ensure the local APIC is enabled */
enable_lapic();
/* Get the device path of the boot CPU */
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index ff32015..baa3599 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -81,7 +81,7 @@ struct mp_params {
int num_cpus; /* Total cpus include BSP */
int parallel_microcode_load;
const void *microcode_pointer;
- /* adjust_apic_id() is called for every potential apic id in the
+ /* adjust_apic_id() is called for every potential APIC id in the
* system up from 0 to CONFIG_MAX_CPUS. Return adjusted apic_id. */
int (*adjust_apic_id)(int index, int apic_id);
/* Flight plan for APs and BSP. */
@@ -134,7 +134,7 @@ struct cpu_map {
int apic_id;
};
-/* Keep track of apic and device structure for each cpu. */
+/* Keep track of APIC and device structure for each CPU. */
static struct cpu_map cpus[CONFIG_MAX_CPUS];
static inline void barrier_wait(atomic_t *b)
@@ -192,7 +192,7 @@ static void asmlinkage ap_init(unsigned int cpu)
struct cpu_info *info;
int apic_id;
- /* Ensure the local apic is enabled */
+ /* Ensure the local APIC is enabled */
enable_lapic();
info = cpu_info();
@@ -546,14 +546,14 @@ static void init_bsp(struct bus *cpu_bus)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- /* Ensure the local apic is enabled */
+ /* Ensure the local APIC is enabled */
enable_lapic();
- /* Set the device path of the boot cpu. */
+ /* Set the device path of the boot CPU. */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = lapicid();
- /* Find the device structure for the boot cpu. */
+ /* Find the device structure for the boot CPU. */
info = cpu_info();
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
@@ -641,7 +641,7 @@ static void mp_initialize_cpu(void)
cpu_initialize(info->index);
}
-/* Returns apic id for coreboot CPU number or < 0 on failure. */
+/* Returns APIC id for coreboot CPU number or < 0 on failure. */
static int mp_get_apic_id(int cpu_slot)
{
if (cpu_slot >= CONFIG_MAX_CPUS || cpu_slot < 0)
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index 09ddb03..139bce1 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -41,7 +41,7 @@ struct smm_stub_params {
/*
* The stub is the entry point that sets up protected mode and stacks for each
- * cpu. It then calls into the SMM handler module. It is encoded as an rmodule.
+ * CPU. It then calls into the SMM handler module. It is encoded as an rmodule.
*/
extern unsigned char _binary_smmstub_start[];
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 2502df8..2fe0156 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -125,7 +125,7 @@ smm_relocate:
shr $24, %ecx
/* calculate offset by multiplying the
- * apic ID by 1024 (0x400)
+ * APIC ID by 1024 (0x400)
*/
movl %ecx, %edx
shl $10, %edx
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